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a,\n    input [31:0] b,\n    input choose,\n    output reg [31:0] z\n    );\n    always @(*)\n    begin\n    case(choose)\n        1'b1:z \u003C= b;\n        1'b0:z \u003C= a;\n   endcase\n   end\nendmodule\n","verilog","",[191,192,193,201,207,213,219,225,231,237,243,249,255,261,267,273,279],"code",{"__ignoreMap":189},[194,195,198],"span",{"class":196,"line":197},"line",1,[194,199,200],{},"`timescale 1ns \u002F 1ns\n",[194,202,204],{"class":196,"line":203},2,[194,205,206],{},"module mux(\n",[194,208,210],{"class":196,"line":209},3,[194,211,212],{},"    input [31:0] a,\n",[194,214,216],{"class":196,"line":215},4,[194,217,218],{},"    input [31:0] b,\n",[194,220,222],{"class":196,"line":221},5,[194,223,224],{},"    input choose,\n",[194,226,228],{"class":196,"line":227},6,[194,229,230],{},"    output reg [31:0] z\n",[194,232,234],{"class":196,"line":233},7,[194,235,236],{},"    );\n",[194,238,240],{"class":196,"line":239},8,[194,241,242],{},"    always @(*)\n",[194,244,246],{"class":196,"line":245},9,[194,247,248],{},"    begin\n",[194,250,252],{"class":196,"line":251},10,[194,253,254],{},"    case(choose)\n",[194,256,258],{"class":196,"line":257},11,[194,259,260],{},"        1'b1:z \u003C= b;\n",[194,262,264],{"class":196,"line":263},12,[194,265,266],{},"        1'b0:z \u003C= a;\n",[194,268,270],{"class":196,"line":269},13,[194,271,272],{},"   endcase\n",[194,274,276],{"class":196,"line":275},14,[194,277,278],{},"   end\n",[194,280,282],{"class":196,"line":281},15,[194,283,284],{},"endmodule\n",[157,286,287],{},[160,288,289],{},"mux5",[184,291,293],{"className":186,"code":292,"language":188,"meta":189,"style":189},"`timescale 1ns \u002F 1ns\nmodule mux5(\n    input [4:0] a,\n    input [4:0] b,\n    input [1:0] choose,\n    output [4:0] z\n    );\n    reg [4:0] t_z;\n    always @(*)\n    begin\n    case(choose)\n        2'b01:t_z \u003C= b;\n        2'b00:t_z \u003C= a;\n        2'b10:t_z \u003C= 5'b11111;\n        2'b11:t_z \u003C= 5'b11111;\n        default:t_z \u003C= 5'bz;\n    endcase\n    end\n    assign z = t_z;\nendmodule\n",[191,294,295,299,304,309,314,319,324,328,333,337,341,345,350,355,360,365,371,377,383,389],{"__ignoreMap":189},[194,296,297],{"class":196,"line":197},[194,298,200],{},[194,300,301],{"class":196,"line":203},[194,302,303],{},"module mux5(\n",[194,305,306],{"class":196,"line":209},[194,307,308],{},"    input [4:0] a,\n",[194,310,311],{"class":196,"line":215},[194,312,313],{},"    input [4:0] b,\n",[194,315,316],{"class":196,"line":221},[194,317,318],{},"    input [1:0] choose,\n",[194,320,321],{"class":196,"line":227},[194,322,323],{},"    output [4:0] z\n",[194,325,326],{"class":196,"line":233},[194,327,236],{},[194,329,330],{"class":196,"line":239},[194,331,332],{},"    reg [4:0] t_z;\n",[194,334,335],{"class":196,"line":245},[194,336,242],{},[194,338,339],{"class":196,"line":251},[194,340,248],{},[194,342,343],{"class":196,"line":257},[194,344,254],{},[194,346,347],{"class":196,"line":263},[194,348,349],{},"        2'b01:t_z \u003C= b;\n",[194,351,352],{"class":196,"line":269},[194,353,354],{},"        2'b00:t_z \u003C= a;\n",[194,356,357],{"class":196,"line":275},[194,358,359],{},"        2'b10:t_z \u003C= 5'b11111;\n",[194,361,362],{"class":196,"line":281},[194,363,364],{},"        2'b11:t_z \u003C= 5'b11111;\n",[194,366,368],{"class":196,"line":367},16,[194,369,370],{},"        default:t_z \u003C= 5'bz;\n",[194,372,374],{"class":196,"line":373},17,[194,375,376],{},"    endcase\n",[194,378,380],{"class":196,"line":379},18,[194,381,382],{},"    end\n",[194,384,386],{"class":196,"line":385},19,[194,387,388],{},"    assign z = t_z;\n",[194,390,392],{"class":196,"line":391},20,[194,393,284],{},[157,395,396],{},[160,397,398],{},"extend5",[184,400,402],{"className":186,"code":401,"language":188,"meta":189,"style":189},"`timescale 1ns \u002F 1ns\nmodule extend5 #(parameter WIDTH = 5)(\n    input [WIDTH - 1:0] a,\n    output [31:0] b\n    );\n    assign b = {{(32 - WIDTH){1'b0}},a};\nendmodule\n",[191,403,404,408,413,418,423,427,432],{"__ignoreMap":189},[194,405,406],{"class":196,"line":197},[194,407,200],{},[194,409,410],{"class":196,"line":203},[194,411,412],{},"module extend5 #(parameter WIDTH = 5)(\n",[194,414,415],{"class":196,"line":209},[194,416,417],{},"    input [WIDTH - 1:0] a,\n",[194,419,420],{"class":196,"line":215},[194,421,422],{},"    output [31:0] b\n",[194,424,425],{"class":196,"line":221},[194,426,236],{},[194,428,429],{"class":196,"line":227},[194,430,431],{},"    assign b = {{(32 - WIDTH){1'b0}},a};\n",[194,433,434],{"class":196,"line":233},[194,435,284],{},[157,437,438],{},[160,439,440],{},"extend16",[184,442,444],{"className":186,"code":443,"language":188,"meta":189,"style":189},"`timescale 1ns \u002F 1ns\nmodule extend16 #(parameter WIDTH = 16)(\n    input [WIDTH - 1:0] a,\n    input sext,             \u002F\u002F1表示有符号\n    output [31:0] b\n    );\n    assign b = sext ? {{(32 - WIDTH){a[WIDTH - 1]}},a} : {{(32 - WIDTH){1'b0}},a};\nendmodule\n",[191,445,446,450,455,459,464,468,472,477],{"__ignoreMap":189},[194,447,448],{"class":196,"line":197},[194,449,200],{},[194,451,452],{"class":196,"line":203},[194,453,454],{},"module extend16 #(parameter WIDTH = 16)(\n",[194,456,457],{"class":196,"line":209},[194,458,417],{},[194,460,461],{"class":196,"line":215},[194,462,463],{},"    input sext,             \u002F\u002F1表示有符号\n",[194,465,466],{"class":196,"line":221},[194,467,422],{},[194,469,470],{"class":196,"line":227},[194,471,236],{},[194,473,474],{"class":196,"line":233},[194,475,476],{},"    assign b = sext ? {{(32 - WIDTH){a[WIDTH - 1]}},a} : {{(32 - WIDTH){1'b0}},a};\n",[194,478,479],{"class":196,"line":239},[194,480,284],{},[157,482,483],{},[160,484,485],{},"extend18",[184,487,489],{"className":186,"code":488,"language":188,"meta":189,"style":189},"`timescale 1ns \u002F 1ns\nmodule extend18 (\n    input [15:0] a,\n    output [31:0] b\n    );\n    assign b = {{(32 - 18){a[15]}},a,2'b00};\nendmodule\n",[191,490,491,495,500,505,509,513,518],{"__ignoreMap":189},[194,492,493],{"class":196,"line":197},[194,494,200],{},[194,496,497],{"class":196,"line":203},[194,498,499],{},"module extend18 (\n",[194,501,502],{"class":196,"line":209},[194,503,504],{},"    input [15:0] a,\n",[194,506,507],{"class":196,"line":215},[194,508,422],{},[194,510,511],{"class":196,"line":221},[194,512,236],{},[194,514,515],{"class":196,"line":227},[194,516,517],{},"    assign b = {{(32 - 18){a[15]}},a,2'b00};\n",[194,519,520],{"class":196,"line":233},[194,521,284],{},[157,523,524],{},[160,525,526],{},"add",[184,528,530],{"className":186,"code":529,"language":188,"meta":189,"style":189},"\n`timescale 1ns \u002F 1ns\nmodule add(\n    input [31:0] a,\n    input [31:0] b,\n    output [31:0] r,\n    output overflow\n    );\n    assign r=a+b;\n    assign overflow=(a[31]==b[31]&&a[31]!=r[31])?1:0;\nendmodule\n",[191,531,532,538,542,547,551,555,560,565,569,574,579],{"__ignoreMap":189},[194,533,534],{"class":196,"line":197},[194,535,537],{"emptyLinePlaceholder":536},true,"\n",[194,539,540],{"class":196,"line":203},[194,541,200],{},[194,543,544],{"class":196,"line":209},[194,545,546],{},"module add(\n",[194,548,549],{"class":196,"line":215},[194,550,212],{},[194,552,553],{"class":196,"line":221},[194,554,218],{},[194,556,557],{"class":196,"line":227},[194,558,559],{},"    output [31:0] r,\n",[194,561,562],{"class":196,"line":233},[194,563,564],{},"    output overflow\n",[194,566,567],{"class":196,"line":239},[194,568,236],{},[194,570,571],{"class":196,"line":245},[194,572,573],{},"    assign r=a+b;\n",[194,575,576],{"class":196,"line":251},[194,577,578],{},"    assign overflow=(a[31]==b[31]&&a[31]!=r[31])?1:0;\n",[194,580,581],{"class":196,"line":257},[194,582,284],{},[157,584,585],{},[160,586,587],{},"add8（是+4没错）",[184,589,591],{"className":186,"code":590,"language":188,"meta":189,"style":189},"`timescale 1ns \u002F 1ns\nmodule add8(\n    input [31:0] a,\n    output [31:0] r\n    );\n    assign r=a+4;\nendmodule\n",[191,592,593,597,602,606,611,615,620],{"__ignoreMap":189},[194,594,595],{"class":196,"line":197},[194,596,200],{},[194,598,599],{"class":196,"line":203},[194,600,601],{},"module add8(\n",[194,603,604],{"class":196,"line":209},[194,605,212],{},[194,607,608],{"class":196,"line":215},[194,609,610],{},"    output [31:0] r\n",[194,612,613],{"class":196,"line":221},[194,614,236],{},[194,616,617],{"class":196,"line":227},[194,618,619],{},"    assign r=a+4;\n",[194,621,622],{"class":196,"line":233},[194,623,284],{},[157,625,626],{},[160,627,628],{},"npc",[184,630,632],{"className":186,"code":631,"language":188,"meta":189,"style":189},"\n`timescale 1ns \u002F 1ns\nmodule npc(\n    input [31:0] a,\n    input rst,\n    output [31:0] r\n    );\n    assign r = rst ? a : a+4;\nendmodule\n",[191,633,634,638,642,647,651,656,660,664,669],{"__ignoreMap":189},[194,635,636],{"class":196,"line":197},[194,637,537],{"emptyLinePlaceholder":536},[194,639,640],{"class":196,"line":203},[194,641,200],{},[194,643,644],{"class":196,"line":209},[194,645,646],{},"module npc(\n",[194,648,649],{"class":196,"line":215},[194,650,212],{},[194,652,653],{"class":196,"line":221},[194,654,655],{},"    input rst,\n",[194,657,658],{"class":196,"line":227},[194,659,610],{},[194,661,662],{"class":196,"line":233},[194,663,236],{},[194,665,666],{"class":196,"line":239},[194,667,668],{},"    assign r = rst ? a : a+4;\n",[194,670,671],{"class":196,"line":245},[194,672,284],{},[157,674,675],{},[160,676,677],{},"pcreg（可以改进）",[184,679,681],{"className":186,"code":680,"language":188,"meta":189,"style":189},"\n`timescale 1ns \u002F 1ns\nmodule pcreg(\n    input clk,  \u002F\u002F1 位输入，寄存器时钟信号，下降沿时为 PC 寄存器赋值\n    input rst,  \u002F\u002F1 位输入，异步重置信号，高电平时将 PC 寄存器清零\n                \u002F\u002F注：当 ena 信号无效时，rst 也可以重置寄存器\n    input ena,  \u002F\u002F1 位输入,有效信号高电平时 PC 寄存器读入 data_in的值，否则保持原有输出\n    input [31:0] data_in,   \u002F\u002F32 位输入，输入数据将被存入寄存器内部\n    output [31:0] data_out  \u002F\u002F32 位输出，工作时始终输出 PC寄存器内部存储的值\n    );\n    D_FF D0 (clk,data_in[0],ena,rst,data_out[0]);\n    D_FF D1 (clk,data_in[1],ena,rst,data_out[1]);\n    D_FF D2 (clk,data_in[2],ena,rst,data_out[2]);\n    D_FF D3 (clk,data_in[3],ena,rst,data_out[3]);\n    D_FF D4 (clk,data_in[4],ena,rst,data_out[4]);\n    D_FF D5 (clk,data_in[5],ena,rst,data_out[5]);\n    D_FF D6 (clk,data_in[6],ena,rst,data_out[6]);\n    D_FF D7 (clk,data_in[7],ena,rst,data_out[7]);\n    D_FF D8 (clk,data_in[8],ena,rst,data_out[8]);\n    D_FF D9 (clk,data_in[9],ena,rst,data_out[9]);\n    D_FF D10 (clk,data_in[10],ena,rst,data_out[10]);\n    D_FF D11 (clk,data_in[11],ena,rst,data_out[11]);\n    D_FF D12 (clk,data_in[12],ena,rst,data_out[12]);\n    D_FF D13 (clk,data_in[13],ena,rst,data_out[13]);\n    D_FF D14 (clk,data_in[14],ena,rst,data_out[14]);\n    D_FF D15 (clk,data_in[15],ena,rst,data_out[15]);\n    D_FF D16 (clk,data_in[16],ena,rst,data_out[16]);\n    D_FF D17 (clk,data_in[17],ena,rst,data_out[17]);\n    D_FF D18 (clk,data_in[18],ena,rst,data_out[18]);\n    D_FF D19 (clk,data_in[19],ena,rst,data_out[19]);\n    D_FF D20 (clk,data_in[20],ena,rst,data_out[20]);\n    D_FF D21 (clk,data_in[21],ena,rst,data_out[21]);\n    D_FF1 D22 (clk,data_in[22],ena,rst,data_out[22]);     \u002F\u002F以00400000为基地址\n    \u002F\u002FD_FF D22 (clk,data_in[22],ena,rst,data_out[22]);    \u002F\u002F以00000000为基地址\n    D_FF D23 (clk,data_in[23],ena,rst,data_out[23]);\n    D_FF D24 (clk,data_in[24],ena,rst,data_out[24]);\n    D_FF D25 (clk,data_in[25],ena,rst,data_out[25]);\n    D_FF D26 (clk,data_in[26],ena,rst,data_out[26]);\n    D_FF D27 (clk,data_in[27],ena,rst,data_out[27]);\n    D_FF D28 (clk,data_in[28],ena,rst,data_out[28]);\n    D_FF D29 (clk,data_in[29],ena,rst,data_out[29]);\n    D_FF D30 (clk,data_in[30],ena,rst,data_out[30]);\n    D_FF D31 (clk,data_in[31],ena,rst,data_out[31]);   \nendmodule\n\nmodule D_FF1(\n    input CLK,      \u002F\u002F时钟信号，下降沿有效\n    input D,        \u002F\u002F输入信号 D\n    input ENA,\n    input RST_n,    \u002F\u002F复位信号，高电平有效\n    output reg Q1   \u002F\u002F输出信号 Q\n    );\n    \n    always @(posedge RST_n or posedge CLK) \n    begin\n      if(RST_n==1)\n        Q1 \u003C= 1;\n      else\n        begin\n        if(ENA==1)\n          Q1 \u003C= D;\n        end\n    end\nendmodule\n",[191,682,683,687,691,696,701,706,711,716,721,726,730,735,740,745,750,755,760,765,770,775,780,786,792,798,804,810,816,822,828,834,840,846,852,858,867,873,879,885,891,897,903,909,915,921,926,931,937,943,949,955,961,967,972,978,984,989,995,1001,1007,1013,1019,1025,1031,1036],{"__ignoreMap":189},[194,684,685],{"class":196,"line":197},[194,686,537],{"emptyLinePlaceholder":536},[194,688,689],{"class":196,"line":203},[194,690,200],{},[194,692,693],{"class":196,"line":209},[194,694,695],{},"module pcreg(\n",[194,697,698],{"class":196,"line":215},[194,699,700],{},"    input clk,  \u002F\u002F1 位输入，寄存器时钟信号，下降沿时为 PC 寄存器赋值\n",[194,702,703],{"class":196,"line":221},[194,704,705],{},"    input rst,  \u002F\u002F1 位输入，异步重置信号，高电平时将 PC 寄存器清零\n",[194,707,708],{"class":196,"line":227},[194,709,710],{},"                \u002F\u002F注：当 ena 信号无效时，rst 也可以重置寄存器\n",[194,712,713],{"class":196,"line":233},[194,714,715],{},"    input ena,  \u002F\u002F1 位输入,有效信号高电平时 PC 寄存器读入 data_in的值，否则保持原有输出\n",[194,717,718],{"class":196,"line":239},[194,719,720],{},"    input [31:0] data_in,   \u002F\u002F32 位输入，输入数据将被存入寄存器内部\n",[194,722,723],{"class":196,"line":245},[194,724,725],{},"    output [31:0] data_out  \u002F\u002F32 位输出，工作时始终输出 PC寄存器内部存储的值\n",[194,727,728],{"class":196,"line":251},[194,729,236],{},[194,731,732],{"class":196,"line":257},[194,733,734],{},"    D_FF D0 (clk,data_in[0],ena,rst,data_out[0]);\n",[194,736,737],{"class":196,"line":263},[194,738,739],{},"    D_FF D1 (clk,data_in[1],ena,rst,data_out[1]);\n",[194,741,742],{"class":196,"line":269},[194,743,744],{},"    D_FF D2 (clk,data_in[2],ena,rst,data_out[2]);\n",[194,746,747],{"class":196,"line":275},[194,748,749],{},"    D_FF D3 (clk,data_in[3],ena,rst,data_out[3]);\n",[194,751,752],{"class":196,"line":281},[194,753,754],{},"    D_FF D4 (clk,data_in[4],ena,rst,data_out[4]);\n",[194,756,757],{"class":196,"line":367},[194,758,759],{},"    D_FF D5 (clk,data_in[5],ena,rst,data_out[5]);\n",[194,761,762],{"class":196,"line":373},[194,763,764],{},"    D_FF D6 (clk,data_in[6],ena,rst,data_out[6]);\n",[194,766,767],{"class":196,"line":379},[194,768,769],{},"    D_FF D7 (clk,data_in[7],ena,rst,data_out[7]);\n",[194,771,772],{"class":196,"line":385},[194,773,774],{},"    D_FF D8 (clk,data_in[8],ena,rst,data_out[8]);\n",[194,776,777],{"class":196,"line":391},[194,778,779],{},"    D_FF D9 (clk,data_in[9],ena,rst,data_out[9]);\n",[194,781,783],{"class":196,"line":782},21,[194,784,785],{},"    D_FF D10 (clk,data_in[10],ena,rst,data_out[10]);\n",[194,787,789],{"class":196,"line":788},22,[194,790,791],{},"    D_FF D11 (clk,data_in[11],ena,rst,data_out[11]);\n",[194,793,795],{"class":196,"line":794},23,[194,796,797],{},"    D_FF D12 (clk,data_in[12],ena,rst,data_out[12]);\n",[194,799,801],{"class":196,"line":800},24,[194,802,803],{},"    D_FF D13 (clk,data_in[13],ena,rst,data_out[13]);\n",[194,805,807],{"class":196,"line":806},25,[194,808,809],{},"    D_FF D14 (clk,data_in[14],ena,rst,data_out[14]);\n",[194,811,813],{"class":196,"line":812},26,[194,814,815],{},"    D_FF D15 (clk,data_in[15],ena,rst,data_out[15]);\n",[194,817,819],{"class":196,"line":818},27,[194,820,821],{},"    D_FF D16 (clk,data_in[16],ena,rst,data_out[16]);\n",[194,823,825],{"class":196,"line":824},28,[194,826,827],{},"    D_FF D17 (clk,data_in[17],ena,rst,data_out[17]);\n",[194,829,831],{"class":196,"line":830},29,[194,832,833],{},"    D_FF D18 (clk,data_in[18],ena,rst,data_out[18]);\n",[194,835,837],{"class":196,"line":836},30,[194,838,839],{},"    D_FF D19 (clk,data_in[19],ena,rst,data_out[19]);\n",[194,841,843],{"class":196,"line":842},31,[194,844,845],{},"    D_FF D20 (clk,data_in[20],ena,rst,data_out[20]);\n",[194,847,849],{"class":196,"line":848},32,[194,850,851],{},"    D_FF D21 (clk,data_in[21],ena,rst,data_out[21]);\n",[194,853,855],{"class":196,"line":854},33,[194,856,857],{},"    D_FF1 D22 (clk,data_in[22],ena,rst,data_out[22]);     \u002F\u002F以00400000为基地址\n",[194,859,861,864],{"class":196,"line":860},34,[194,862,863],{},"    \u002F\u002FD_FF D22 (clk,data_in[22],ena,rst,data_out[22]);",[194,865,866],{},"    \u002F\u002F以00000000为基地址\n",[194,868,870],{"class":196,"line":869},35,[194,871,872],{},"    D_FF D23 (clk,data_in[23],ena,rst,data_out[23]);\n",[194,874,876],{"class":196,"line":875},36,[194,877,878],{},"    D_FF D24 (clk,data_in[24],ena,rst,data_out[24]);\n",[194,880,882],{"class":196,"line":881},37,[194,883,884],{},"    D_FF D25 (clk,data_in[25],ena,rst,data_out[25]);\n",[194,886,888],{"class":196,"line":887},38,[194,889,890],{},"    D_FF D26 (clk,data_in[26],ena,rst,data_out[26]);\n",[194,892,894],{"class":196,"line":893},39,[194,895,896],{},"    D_FF D27 (clk,data_in[27],ena,rst,data_out[27]);\n",[194,898,900],{"class":196,"line":899},40,[194,901,902],{},"    D_FF D28 (clk,data_in[28],ena,rst,data_out[28]);\n",[194,904,906],{"class":196,"line":905},41,[194,907,908],{},"    D_FF D29 (clk,data_in[29],ena,rst,data_out[29]);\n",[194,910,912],{"class":196,"line":911},42,[194,913,914],{},"    D_FF D30 (clk,data_in[30],ena,rst,data_out[30]);\n",[194,916,918],{"class":196,"line":917},43,[194,919,920],{},"    D_FF D31 (clk,data_in[31],ena,rst,data_out[31]);   \n",[194,922,924],{"class":196,"line":923},44,[194,925,284],{},[194,927,929],{"class":196,"line":928},45,[194,930,537],{"emptyLinePlaceholder":536},[194,932,934],{"class":196,"line":933},46,[194,935,936],{},"module D_FF1(\n",[194,938,940],{"class":196,"line":939},47,[194,941,942],{},"    input CLK,      \u002F\u002F时钟信号，下降沿有效\n",[194,944,946],{"class":196,"line":945},48,[194,947,948],{},"    input D,        \u002F\u002F输入信号 D\n",[194,950,952],{"class":196,"line":951},49,[194,953,954],{},"    input ENA,\n",[194,956,958],{"class":196,"line":957},50,[194,959,960],{},"    input RST_n,    \u002F\u002F复位信号，高电平有效\n",[194,962,964],{"class":196,"line":963},51,[194,965,966],{},"    output reg Q1   \u002F\u002F输出信号 Q\n",[194,968,970],{"class":196,"line":969},52,[194,971,236],{},[194,973,975],{"class":196,"line":974},53,[194,976,977],{},"    \n",[194,979,981],{"class":196,"line":980},54,[194,982,983],{},"    always @(posedge RST_n or posedge CLK) \n",[194,985,987],{"class":196,"line":986},55,[194,988,248],{},[194,990,992],{"class":196,"line":991},56,[194,993,994],{},"      if(RST_n==1)\n",[194,996,998],{"class":196,"line":997},57,[194,999,1000],{},"        Q1 \u003C= 1;\n",[194,1002,1004],{"class":196,"line":1003},58,[194,1005,1006],{},"      else\n",[194,1008,1010],{"class":196,"line":1009},59,[194,1011,1012],{},"        begin\n",[194,1014,1016],{"class":196,"line":1015},60,[194,1017,1018],{},"        if(ENA==1)\n",[194,1020,1022],{"class":196,"line":1021},61,[194,1023,1024],{},"          Q1 \u003C= D;\n",[194,1026,1028],{"class":196,"line":1027},62,[194,1029,1030],{},"        end\n",[194,1032,1034],{"class":196,"line":1033},63,[194,1035,382],{},[194,1037,1039],{"class":196,"line":1038},64,[194,1040,284],{},[157,1042,1043],{},[160,1044,1045],{},"alu",[184,1047,1049],{"className":186,"code":1048,"language":188,"meta":189,"style":189},"\n`timescale 1ns \u002F 1ns\nmodule alu(\n    input [31:0] a,        \u002F\u002FOP1\n    input [31:0] b,        \u002F\u002FOP2\n    input [3:0] aluc,      \u002F\u002Fcontroller\n    output [31:0] r,       \u002F\u002Fresult\n    output zero,\n    output carry,\n    output negative,\n    output overflow);\n        \n    parameter Addu   =    4'b0000;    \u002F\u002Fr=a+b unsigned\n    parameter Add    =    4'b0010;    \u002F\u002Fr=a+b signed\n    parameter Subu   =    4'b0001;    \u002F\u002Fr=a-b unsigned\n    parameter Sub    =    4'b0011;    \u002F\u002Fr=a-b signed\n    parameter And    =    4'b0100;    \u002F\u002Fr=a&b\n    parameter Or     =    4'b0101;    \u002F\u002Fr=a|b\n    parameter Xor    =    4'b0110;    \u002F\u002Fr=a^b\n    parameter Nor    =    4'b0111;    \u002F\u002Fr=~(a|b)\n    parameter Lui1   =    4'b1000;    \u002F\u002Fr={b[15:0],16'b0}\n    parameter Lui2   =    4'b1001;    \u002F\u002Fr={b[15:0],16'b0}\n    parameter Slt    =    4'b1011;    \u002F\u002Fr=(a-b\u003C0)?1:0 signed\n    parameter Sltu   =    4'b1010;    \u002F\u002Fr=(a-b\u003C0)?1:0 unsigned\n    parameter Sra    =    4'b1100;    \u002F\u002Fr=b>>>a \n    parameter Sll    =    4'b1110;    \u002F\u002Fr=b\u003C\u003Ca\n    parameter Srl    =    4'b1101;    \u002F\u002Fr=b>>a\n    parameter Slr    =    4'b1111;    \u002F\u002Fr=b\u003C\u003Ca\n    \n    parameter bits=31;\n    parameter ENABLE=1,DISABLE=0;\n    \n    reg signed [32:0] result;\n    reg [33:0] sresult;\n    wire signed [31:0] sa=a,sb=b;\n  \n    always@(*)begin\n        case(aluc)\n            Addu: begin\n                result=a+b;\n                sresult={sa[31],sa}+{sb[31],sb};\n            end\n            Subu: begin\n                result=a-b;\n                sresult={sa[31],sa}-{sb[31],sb};\n            end\n            Add: begin\n                result=sa+sb;\n            end\n            Sub: begin\n                result=sa-sb;\n            end\n            Sra: begin\n                if(a==0) {result[31:0],result[32]}={b,1'b0};\n                else {result[31:0],result[32]}=sb>>>(a-1);\n            end\n            Srl: begin\n                if(a==0) {result[31:0],result[32]}={b,1'b0};\n                else {result[31:0],result[32]}=b>>(a-1);\n            end\n            Sll,Slr: begin\n                result=b\u003C\u003Ca;\n            end\n            And: begin\n                result=a&b;\n            end\n            Or: begin\n                result=a|b;\n            end\n            Xor: begin\n                result=a^b;\n            end\n            Nor: begin\n                result=~(a|b);\n            end\n            Sltu: begin\n                result=a\u003Cb?1:0;\n            end\n            Slt: begin\n                result=sa\u003Csb?1:0;\n            end\n            Lui1,Lui2: result = {b[15:0], 16'b0};\n            default:\n                result=a+b;\n        endcase\n    end\n    \n    assign r=result[31:0];\n    assign carry = (aluc==Addu|aluc==Subu|aluc==Sltu|aluc==Sra|aluc==Srl|aluc==Sll)?result[32]:1'bz; \n    assign zero=(r==32'b0)?1:0;\n    assign negative=result[31];\n    assign overflow=(aluc==Add|aluc==Sub)?(sresult[32]^sresult[33]):1'bz;\nendmodule\n",[191,1050,1051,1055,1059,1064,1069,1074,1079,1084,1089,1094,1099,1104,1109,1114,1119,1124,1129,1134,1139,1144,1149,1154,1159,1164,1169,1174,1179,1184,1189,1193,1198,1203,1207,1212,1217,1222,1227,1232,1237,1242,1247,1252,1257,1262,1267,1272,1276,1281,1286,1290,1295,1300,1304,1309,1314,1319,1323,1328,1332,1337,1341,1346,1351,1355,1360,1366,1371,1377,1383,1388,1394,1400,1405,1411,1417,1422,1428,1434,1439,1445,1451,1456,1462,1468,1473,1479,1484,1489,1495,1501,1507,1513,1519],{"__ignoreMap":189},[194,1052,1053],{"class":196,"line":197},[194,1054,537],{"emptyLinePlaceholder":536},[194,1056,1057],{"class":196,"line":203},[194,1058,200],{},[194,1060,1061],{"class":196,"line":209},[194,1062,1063],{},"module alu(\n",[194,1065,1066],{"class":196,"line":215},[194,1067,1068],{},"    input [31:0] a,        \u002F\u002FOP1\n",[194,1070,1071],{"class":196,"line":221},[194,1072,1073],{},"    input [31:0] b,        \u002F\u002FOP2\n",[194,1075,1076],{"class":196,"line":227},[194,1077,1078],{},"    input [3:0] aluc,      \u002F\u002Fcontroller\n",[194,1080,1081],{"class":196,"line":233},[194,1082,1083],{},"    output [31:0] r,       \u002F\u002Fresult\n",[194,1085,1086],{"class":196,"line":239},[194,1087,1088],{},"    output zero,\n",[194,1090,1091],{"class":196,"line":245},[194,1092,1093],{},"    output carry,\n",[194,1095,1096],{"class":196,"line":251},[194,1097,1098],{},"    output negative,\n",[194,1100,1101],{"class":196,"line":257},[194,1102,1103],{},"    output overflow);\n",[194,1105,1106],{"class":196,"line":263},[194,1107,1108],{},"        \n",[194,1110,1111],{"class":196,"line":269},[194,1112,1113],{},"    parameter Addu   =    4'b0000;    \u002F\u002Fr=a+b unsigned\n",[194,1115,1116],{"class":196,"line":275},[194,1117,1118],{},"    parameter Add    =    4'b0010;    \u002F\u002Fr=a+b signed\n",[194,1120,1121],{"class":196,"line":281},[194,1122,1123],{},"    parameter Subu   =    4'b0001;    \u002F\u002Fr=a-b unsigned\n",[194,1125,1126],{"class":196,"line":367},[194,1127,1128],{},"    parameter Sub    =    4'b0011;    \u002F\u002Fr=a-b signed\n",[194,1130,1131],{"class":196,"line":373},[194,1132,1133],{},"    parameter And    =    4'b0100;    \u002F\u002Fr=a&b\n",[194,1135,1136],{"class":196,"line":379},[194,1137,1138],{},"    parameter Or     =    4'b0101;    \u002F\u002Fr=a|b\n",[194,1140,1141],{"class":196,"line":385},[194,1142,1143],{},"    parameter Xor    =    4'b0110;    \u002F\u002Fr=a^b\n",[194,1145,1146],{"class":196,"line":391},[194,1147,1148],{},"    parameter Nor    =    4'b0111;    \u002F\u002Fr=~(a|b)\n",[194,1150,1151],{"class":196,"line":782},[194,1152,1153],{},"    parameter Lui1   =    4'b1000;    \u002F\u002Fr={b[15:0],16'b0}\n",[194,1155,1156],{"class":196,"line":788},[194,1157,1158],{},"    parameter Lui2   =    4'b1001;    \u002F\u002Fr={b[15:0],16'b0}\n",[194,1160,1161],{"class":196,"line":794},[194,1162,1163],{},"    parameter Slt    =    4'b1011;    \u002F\u002Fr=(a-b\u003C0)?1:0 signed\n",[194,1165,1166],{"class":196,"line":800},[194,1167,1168],{},"    parameter Sltu   =    4'b1010;    \u002F\u002Fr=(a-b\u003C0)?1:0 unsigned\n",[194,1170,1171],{"class":196,"line":806},[194,1172,1173],{},"    parameter Sra    =    4'b1100;    \u002F\u002Fr=b>>>a \n",[194,1175,1176],{"class":196,"line":812},[194,1177,1178],{},"    parameter Sll    =    4'b1110;    \u002F\u002Fr=b\u003C\u003Ca\n",[194,1180,1181],{"class":196,"line":818},[194,1182,1183],{},"    parameter Srl    =    4'b1101;    \u002F\u002Fr=b>>a\n",[194,1185,1186],{"class":196,"line":824},[194,1187,1188],{},"    parameter Slr    =    4'b1111;    \u002F\u002Fr=b\u003C\u003Ca\n",[194,1190,1191],{"class":196,"line":830},[194,1192,977],{},[194,1194,1195],{"class":196,"line":836},[194,1196,1197],{},"    parameter bits=31;\n",[194,1199,1200],{"class":196,"line":842},[194,1201,1202],{},"    parameter ENABLE=1,DISABLE=0;\n",[194,1204,1205],{"class":196,"line":848},[194,1206,977],{},[194,1208,1209],{"class":196,"line":854},[194,1210,1211],{},"    reg signed [32:0] result;\n",[194,1213,1214],{"class":196,"line":860},[194,1215,1216],{},"    reg [33:0] sresult;\n",[194,1218,1219],{"class":196,"line":869},[194,1220,1221],{},"    wire signed [31:0] sa=a,sb=b;\n",[194,1223,1224],{"class":196,"line":875},[194,1225,1226],{},"  \n",[194,1228,1229],{"class":196,"line":881},[194,1230,1231],{},"    always@(*)begin\n",[194,1233,1234],{"class":196,"line":887},[194,1235,1236],{},"        case(aluc)\n",[194,1238,1239],{"class":196,"line":893},[194,1240,1241],{},"            Addu: begin\n",[194,1243,1244],{"class":196,"line":899},[194,1245,1246],{},"                result=a+b;\n",[194,1248,1249],{"class":196,"line":905},[194,1250,1251],{},"                sresult={sa[31],sa}+{sb[31],sb};\n",[194,1253,1254],{"class":196,"line":911},[194,1255,1256],{},"            end\n",[194,1258,1259],{"class":196,"line":917},[194,1260,1261],{},"            Subu: begin\n",[194,1263,1264],{"class":196,"line":923},[194,1265,1266],{},"                result=a-b;\n",[194,1268,1269],{"class":196,"line":928},[194,1270,1271],{},"                sresult={sa[31],sa}-{sb[31],sb};\n",[194,1273,1274],{"class":196,"line":933},[194,1275,1256],{},[194,1277,1278],{"class":196,"line":939},[194,1279,1280],{},"            Add: begin\n",[194,1282,1283],{"class":196,"line":945},[194,1284,1285],{},"                result=sa+sb;\n",[194,1287,1288],{"class":196,"line":951},[194,1289,1256],{},[194,1291,1292],{"class":196,"line":957},[194,1293,1294],{},"            Sub: begin\n",[194,1296,1297],{"class":196,"line":963},[194,1298,1299],{},"                result=sa-sb;\n",[194,1301,1302],{"class":196,"line":969},[194,1303,1256],{},[194,1305,1306],{"class":196,"line":974},[194,1307,1308],{},"            Sra: begin\n",[194,1310,1311],{"class":196,"line":980},[194,1312,1313],{},"                if(a==0) {result[31:0],result[32]}={b,1'b0};\n",[194,1315,1316],{"class":196,"line":986},[194,1317,1318],{},"                else {result[31:0],result[32]}=sb>>>(a-1);\n",[194,1320,1321],{"class":196,"line":991},[194,1322,1256],{},[194,1324,1325],{"class":196,"line":997},[194,1326,1327],{},"            Srl: begin\n",[194,1329,1330],{"class":196,"line":1003},[194,1331,1313],{},[194,1333,1334],{"class":196,"line":1009},[194,1335,1336],{},"                else {result[31:0],result[32]}=b>>(a-1);\n",[194,1338,1339],{"class":196,"line":1015},[194,1340,1256],{},[194,1342,1343],{"class":196,"line":1021},[194,1344,1345],{},"            Sll,Slr: begin\n",[194,1347,1348],{"class":196,"line":1027},[194,1349,1350],{},"                result=b\u003C\u003Ca;\n",[194,1352,1353],{"class":196,"line":1033},[194,1354,1256],{},[194,1356,1357],{"class":196,"line":1038},[194,1358,1359],{},"            And: begin\n",[194,1361,1363],{"class":196,"line":1362},65,[194,1364,1365],{},"                result=a&b;\n",[194,1367,1369],{"class":196,"line":1368},66,[194,1370,1256],{},[194,1372,1374],{"class":196,"line":1373},67,[194,1375,1376],{},"            Or: begin\n",[194,1378,1380],{"class":196,"line":1379},68,[194,1381,1382],{},"                result=a|b;\n",[194,1384,1386],{"class":196,"line":1385},69,[194,1387,1256],{},[194,1389,1391],{"class":196,"line":1390},70,[194,1392,1393],{},"            Xor: begin\n",[194,1395,1397],{"class":196,"line":1396},71,[194,1398,1399],{},"                result=a^b;\n",[194,1401,1403],{"class":196,"line":1402},72,[194,1404,1256],{},[194,1406,1408],{"class":196,"line":1407},73,[194,1409,1410],{},"            Nor: begin\n",[194,1412,1414],{"class":196,"line":1413},74,[194,1415,1416],{},"                result=~(a|b);\n",[194,1418,1420],{"class":196,"line":1419},75,[194,1421,1256],{},[194,1423,1425],{"class":196,"line":1424},76,[194,1426,1427],{},"            Sltu: begin\n",[194,1429,1431],{"class":196,"line":1430},77,[194,1432,1433],{},"                result=a\u003Cb?1:0;\n",[194,1435,1437],{"class":196,"line":1436},78,[194,1438,1256],{},[194,1440,1442],{"class":196,"line":1441},79,[194,1443,1444],{},"            Slt: begin\n",[194,1446,1448],{"class":196,"line":1447},80,[194,1449,1450],{},"                result=sa\u003Csb?1:0;\n",[194,1452,1454],{"class":196,"line":1453},81,[194,1455,1256],{},[194,1457,1459],{"class":196,"line":1458},82,[194,1460,1461],{},"            Lui1,Lui2: result = {b[15:0], 16'b0};\n",[194,1463,1465],{"class":196,"line":1464},83,[194,1466,1467],{},"            default:\n",[194,1469,1471],{"class":196,"line":1470},84,[194,1472,1246],{},[194,1474,1476],{"class":196,"line":1475},85,[194,1477,1478],{},"        endcase\n",[194,1480,1482],{"class":196,"line":1481},86,[194,1483,382],{},[194,1485,1487],{"class":196,"line":1486},87,[194,1488,977],{},[194,1490,1492],{"class":196,"line":1491},88,[194,1493,1494],{},"    assign r=result[31:0];\n",[194,1496,1498],{"class":196,"line":1497},89,[194,1499,1500],{},"    assign carry = (aluc==Addu|aluc==Subu|aluc==Sltu|aluc==Sra|aluc==Srl|aluc==Sll)?result[32]:1'bz; \n",[194,1502,1504],{"class":196,"line":1503},90,[194,1505,1506],{},"    assign zero=(r==32'b0)?1:0;\n",[194,1508,1510],{"class":196,"line":1509},91,[194,1511,1512],{},"    assign negative=result[31];\n",[194,1514,1516],{"class":196,"line":1515},92,[194,1517,1518],{},"    assign overflow=(aluc==Add|aluc==Sub)?(sresult[32]^sresult[33]):1'bz;\n",[194,1520,1522],{"class":196,"line":1521},93,[194,1523,284],{},[157,1525,1526],{},[160,1527,1528],{},"regfile(可以改进)",[184,1530,1532],{"className":186,"code":1531,"language":188,"meta":189,"style":189},"\n`timescale 1ns \u002F 1ns\nmodule regfile(\n    input clk, \u002F\u002F寄存器组时钟信号，下降沿写入数据\n    input rst, \u002F\u002Freset 信号，异步复位，高电平时全部寄存器置零\n    input we,  \u002F\u002F寄存器读写有效信号，高电平时允许寄存器写入数据，低电平时允许寄存器读出数据\n    input ov,\n    input [4:0] raddr1,   \u002F\u002F所需读取的寄存器的地址\n    input [4:0] raddr2,   \u002F\u002F所需读取的寄存器的地址\n    input [4:0] waddr,    \u002F\u002F写寄存器的地址\n    input [31:0] wdata,   \u002F\u002F写寄存器数据，数据在 clk 下降沿时被写入\n    output [31:0] rdata1, \u002F\u002Fraddr1 所对应寄存器的输出数据\n    output [31:0] rdata2  \u002F\u002Fraddr2 所对应寄存器的输出数据\n    );\n    wire [31:0] switch;\n    wire [31:0] array_reg [31:0];\n    reg c_o;\n    always@(ov)\n    begin\n    case(ov)\n    1'bz:c_o = 1;\n    1'b1:c_o = 0;\n    1'b0:c_o = 1;\n    default:c_o=1;\n    endcase\n    end\n    Decoder dec (waddr,we&c_o,switch);\n    assign array_reg[0] = 0;\n    Pcreg Reg2 (clk,rst,switch[1],wdata,array_reg[1]);\n    Pcreg Reg3 (clk,rst,switch[2],wdata,array_reg[2]);\n    Pcreg Reg4 (clk,rst,switch[3],wdata,array_reg[3]);\n    Pcreg Reg5 (clk,rst,switch[4],wdata,array_reg[4]);\n    Pcreg Reg6 (clk,rst,switch[5],wdata,array_reg[5]);\n    Pcreg Reg7 (clk,rst,switch[6],wdata,array_reg[6]);\n    Pcreg Reg8 (clk,rst,switch[7],wdata,array_reg[7]);\n    Pcreg Reg9 (clk,rst,switch[8],wdata,array_reg[8]);\n    Pcreg Reg10 (clk,rst,switch[9],wdata,array_reg[9]);\n    Pcreg Reg11 (clk,rst,switch[10],wdata,array_reg[10]);\n    Pcreg Reg12 (clk,rst,switch[11],wdata,array_reg[11]);\n    Pcreg Reg13 (clk,rst,switch[12],wdata,array_reg[12]);\n    Pcreg Reg14 (clk,rst,switch[13],wdata,array_reg[13]);\n    Pcreg Reg15 (clk,rst,switch[14],wdata,array_reg[14]);\n    Pcreg Reg16 (clk,rst,switch[15],wdata,array_reg[15]);\n    Pcreg Reg17 (clk,rst,switch[16],wdata,array_reg[16]);\n    Pcreg Reg18 (clk,rst,switch[17],wdata,array_reg[17]);\n    Pcreg Reg19 (clk,rst,switch[18],wdata,array_reg[18]);\n    Pcreg Reg20 (clk,rst,switch[19],wdata,array_reg[19]);\n    Pcreg Reg21 (clk,rst,switch[20],wdata,array_reg[20]);\n    Pcreg Reg22 (clk,rst,switch[21],wdata,array_reg[21]);\n    Pcreg Reg23 (clk,rst,switch[22],wdata,array_reg[22]);\n    Pcreg Reg24 (clk,rst,switch[23],wdata,array_reg[23]);\n    Pcreg Reg25 (clk,rst,switch[24],wdata,array_reg[24]);\n    Pcreg Reg26 (clk,rst,switch[25],wdata,array_reg[25]);\n    Pcreg Reg27 (clk,rst,switch[26],wdata,array_reg[26]);\n    Pcreg Reg28 (clk,rst,switch[27],wdata,array_reg[27]);\n    Pcreg Reg29 (clk,rst,switch[28],wdata,array_reg[28]);\n    Pcreg Reg30 (clk,rst,switch[29],wdata,array_reg[29]);\n    Pcreg Reg31 (clk,rst,switch[30],wdata,array_reg[30]);\n    Pcreg Reg32 (clk,rst,switch[31],wdata,array_reg[31]);\n    assign rdata1 = array_reg[raddr1];\n    assign rdata2 = array_reg[raddr2];\nendmodule\n\nmodule Decoder(\n    input [4:0] iData,      \n    input  iEna,            \n    output [31:0] oData      \n    );        \n    assign oData=(iEna==1)?(32'b00000000000000000000000000000001\u003C\u003CiData):32'bx;\nendmodule\n\nmodule Pcreg(\n    input clk,  \u002F\u002F1 位输入，寄存器时钟信号，下降沿时为 PC 寄存器赋值\n    input rst,  \u002F\u002F1 位输入，异步重置信号，高电平时将 PC 寄存器清零\n                \u002F\u002F注：当 ena 信号无效时，rst 也可以重置寄存器\n    input ena,  \u002F\u002F1 位输入,有效信号高电平时 PC 寄存器读入 data_in的值，否则保持原有输出\n    input [31:0] data_in,   \u002F\u002F32 位输入，输入数据将被存入寄存器内部\n    output [31:0] data_out  \u002F\u002F32 位输出，工作时始终输出 PC寄存器内部存储的值\n    );\n    \n    D_FF d0 (clk,data_in[0],ena,rst,data_out[0]);\n    D_FF d1 (clk,data_in[1],ena,rst,data_out[1]);\n    D_FF d2 (clk,data_in[2],ena,rst,data_out[2]);\n    D_FF d3 (clk,data_in[3],ena,rst,data_out[3]);\n    D_FF d4 (clk,data_in[4],ena,rst,data_out[4]);\n    D_FF d5 (clk,data_in[5],ena,rst,data_out[5]);\n    D_FF d6 (clk,data_in[6],ena,rst,data_out[6]);\n    D_FF d7 (clk,data_in[7],ena,rst,data_out[7]);\n    D_FF d8 (clk,data_in[8],ena,rst,data_out[8]);\n    D_FF d9 (clk,data_in[9],ena,rst,data_out[9]);\n    D_FF d10 (clk,data_in[10],ena,rst,data_out[10]);\n    D_FF d11 (clk,data_in[11],ena,rst,data_out[11]);\n    D_FF d12 (clk,data_in[12],ena,rst,data_out[12]);\n    D_FF d13 (clk,data_in[13],ena,rst,data_out[13]);\n    D_FF d14 (clk,data_in[14],ena,rst,data_out[14]);\n    D_FF d15 (clk,data_in[15],ena,rst,data_out[15]);\n    D_FF d16 (clk,data_in[16],ena,rst,data_out[16]);\n    D_FF d17 (clk,data_in[17],ena,rst,data_out[17]);\n    D_FF d18 (clk,data_in[18],ena,rst,data_out[18]);\n    D_FF d19 (clk,data_in[19],ena,rst,data_out[19]);\n    D_FF d20 (clk,data_in[20],ena,rst,data_out[20]);\n    D_FF d21 (clk,data_in[21],ena,rst,data_out[21]);\n    D_FF d22 (clk,data_in[22],ena,rst,data_out[22]);\n    D_FF d23 (clk,data_in[23],ena,rst,data_out[23]);\n    D_FF d24 (clk,data_in[24],ena,rst,data_out[24]);\n    D_FF d25 (clk,data_in[25],ena,rst,data_out[25]);\n    D_FF d26 (clk,data_in[26],ena,rst,data_out[26]);\n    D_FF d27 (clk,data_in[27],ena,rst,data_out[27]);\n    D_FF d28 (clk,data_in[28],ena,rst,data_out[28]);\n    D_FF d29 (clk,data_in[29],ena,rst,data_out[29]);\n    D_FF d30 (clk,data_in[30],ena,rst,data_out[30]);\n    D_FF d31 (clk,data_in[31],ena,rst,data_out[31]);   \nendmodule\n\nmodule D_FF(\n    input CLK,      \u002F\u002F时钟信号，下降沿有效\n    input D,        \u002F\u002F输入信号 D\n    input ENA,\n    input RST_n,    \u002F\u002F复位信号，高电平有效\n    output reg Q1   \u002F\u002F输出信号 Q1\n    );\n    \n    \u002F\u002F 2020\u002F03\u002F29 有小伙伴指出这里可能有问题, negedge CLK, 请以仿真结果为准(博主无法进行仿真了)\n    always @(posedge RST_n or posedge CLK)\n    begin\n      if(RST_n==1)\n        Q1 = 0;\n      else\n      begin\n      if(ENA==1)\n        Q1 = D;\n      end\n    end\nendmodule\n",[191,1533,1534,1538,1542,1547,1552,1557,1562,1567,1572,1577,1582,1587,1592,1597,1601,1606,1611,1616,1621,1625,1630,1635,1640,1645,1650,1654,1658,1663,1668,1673,1678,1683,1688,1693,1698,1703,1708,1713,1718,1723,1728,1733,1738,1743,1748,1753,1758,1763,1768,1773,1778,1783,1788,1793,1798,1803,1808,1813,1818,1823,1828,1833,1837,1841,1846,1851,1856,1861,1866,1871,1875,1879,1884,1888,1892,1896,1900,1904,1908,1912,1916,1921,1926,1931,1936,1941,1946,1951,1956,1961,1966,1971,1976,1981,1987,1993,1999,2005,2011,2017,2023,2029,2035,2041,2047,2053,2059,2065,2071,2077,2083,2089,2095,2100,2105,2111,2116,2121,2126,2131,2137,2142,2147,2153,2159,2164,2169,2175,2180,2186,2192,2198,2204,2209],{"__ignoreMap":189},[194,1535,1536],{"class":196,"line":197},[194,1537,537],{"emptyLinePlaceholder":536},[194,1539,1540],{"class":196,"line":203},[194,1541,200],{},[194,1543,1544],{"class":196,"line":209},[194,1545,1546],{},"module regfile(\n",[194,1548,1549],{"class":196,"line":215},[194,1550,1551],{},"    input clk, \u002F\u002F寄存器组时钟信号，下降沿写入数据\n",[194,1553,1554],{"class":196,"line":221},[194,1555,1556],{},"    input rst, \u002F\u002Freset 信号，异步复位，高电平时全部寄存器置零\n",[194,1558,1559],{"class":196,"line":227},[194,1560,1561],{},"    input we,  \u002F\u002F寄存器读写有效信号，高电平时允许寄存器写入数据，低电平时允许寄存器读出数据\n",[194,1563,1564],{"class":196,"line":233},[194,1565,1566],{},"    input ov,\n",[194,1568,1569],{"class":196,"line":239},[194,1570,1571],{},"    input [4:0] raddr1,   \u002F\u002F所需读取的寄存器的地址\n",[194,1573,1574],{"class":196,"line":245},[194,1575,1576],{},"    input [4:0] raddr2,   \u002F\u002F所需读取的寄存器的地址\n",[194,1578,1579],{"class":196,"line":251},[194,1580,1581],{},"    input [4:0] waddr,    \u002F\u002F写寄存器的地址\n",[194,1583,1584],{"class":196,"line":257},[194,1585,1586],{},"    input [31:0] wdata,   \u002F\u002F写寄存器数据，数据在 clk 下降沿时被写入\n",[194,1588,1589],{"class":196,"line":263},[194,1590,1591],{},"    output [31:0] rdata1, \u002F\u002Fraddr1 所对应寄存器的输出数据\n",[194,1593,1594],{"class":196,"line":269},[194,1595,1596],{},"    output [31:0] rdata2  \u002F\u002Fraddr2 所对应寄存器的输出数据\n",[194,1598,1599],{"class":196,"line":275},[194,1600,236],{},[194,1602,1603],{"class":196,"line":281},[194,1604,1605],{},"    wire [31:0] switch;\n",[194,1607,1608],{"class":196,"line":367},[194,1609,1610],{},"    wire [31:0] array_reg [31:0];\n",[194,1612,1613],{"class":196,"line":373},[194,1614,1615],{},"    reg c_o;\n",[194,1617,1618],{"class":196,"line":379},[194,1619,1620],{},"    always@(ov)\n",[194,1622,1623],{"class":196,"line":385},[194,1624,248],{},[194,1626,1627],{"class":196,"line":391},[194,1628,1629],{},"    case(ov)\n",[194,1631,1632],{"class":196,"line":782},[194,1633,1634],{},"    1'bz:c_o = 1;\n",[194,1636,1637],{"class":196,"line":788},[194,1638,1639],{},"    1'b1:c_o = 0;\n",[194,1641,1642],{"class":196,"line":794},[194,1643,1644],{},"    1'b0:c_o = 1;\n",[194,1646,1647],{"class":196,"line":800},[194,1648,1649],{},"    default:c_o=1;\n",[194,1651,1652],{"class":196,"line":806},[194,1653,376],{},[194,1655,1656],{"class":196,"line":812},[194,1657,382],{},[194,1659,1660],{"class":196,"line":818},[194,1661,1662],{},"    Decoder dec (waddr,we&c_o,switch);\n",[194,1664,1665],{"class":196,"line":824},[194,1666,1667],{},"    assign array_reg[0] = 0;\n",[194,1669,1670],{"class":196,"line":830},[194,1671,1672],{},"    Pcreg Reg2 (clk,rst,switch[1],wdata,array_reg[1]);\n",[194,1674,1675],{"class":196,"line":836},[194,1676,1677],{},"    Pcreg Reg3 (clk,rst,switch[2],wdata,array_reg[2]);\n",[194,1679,1680],{"class":196,"line":842},[194,1681,1682],{},"    Pcreg Reg4 (clk,rst,switch[3],wdata,array_reg[3]);\n",[194,1684,1685],{"class":196,"line":848},[194,1686,1687],{},"    Pcreg Reg5 (clk,rst,switch[4],wdata,array_reg[4]);\n",[194,1689,1690],{"class":196,"line":854},[194,1691,1692],{},"    Pcreg Reg6 (clk,rst,switch[5],wdata,array_reg[5]);\n",[194,1694,1695],{"class":196,"line":860},[194,1696,1697],{},"    Pcreg Reg7 (clk,rst,switch[6],wdata,array_reg[6]);\n",[194,1699,1700],{"class":196,"line":869},[194,1701,1702],{},"    Pcreg Reg8 (clk,rst,switch[7],wdata,array_reg[7]);\n",[194,1704,1705],{"class":196,"line":875},[194,1706,1707],{},"    Pcreg Reg9 (clk,rst,switch[8],wdata,array_reg[8]);\n",[194,1709,1710],{"class":196,"line":881},[194,1711,1712],{},"    Pcreg Reg10 (clk,rst,switch[9],wdata,array_reg[9]);\n",[194,1714,1715],{"class":196,"line":887},[194,1716,1717],{},"    Pcreg Reg11 (clk,rst,switch[10],wdata,array_reg[10]);\n",[194,1719,1720],{"class":196,"line":893},[194,1721,1722],{},"    Pcreg Reg12 (clk,rst,switch[11],wdata,array_reg[11]);\n",[194,1724,1725],{"class":196,"line":899},[194,1726,1727],{},"    Pcreg Reg13 (clk,rst,switch[12],wdata,array_reg[12]);\n",[194,1729,1730],{"class":196,"line":905},[194,1731,1732],{},"    Pcreg Reg14 (clk,rst,switch[13],wdata,array_reg[13]);\n",[194,1734,1735],{"class":196,"line":911},[194,1736,1737],{},"    Pcreg Reg15 (clk,rst,switch[14],wdata,array_reg[14]);\n",[194,1739,1740],{"class":196,"line":917},[194,1741,1742],{},"    Pcreg Reg16 (clk,rst,switch[15],wdata,array_reg[15]);\n",[194,1744,1745],{"class":196,"line":923},[194,1746,1747],{},"    Pcreg Reg17 (clk,rst,switch[16],wdata,array_reg[16]);\n",[194,1749,1750],{"class":196,"line":928},[194,1751,1752],{},"    Pcreg Reg18 (clk,rst,switch[17],wdata,array_reg[17]);\n",[194,1754,1755],{"class":196,"line":933},[194,1756,1757],{},"    Pcreg Reg19 (clk,rst,switch[18],wdata,array_reg[18]);\n",[194,1759,1760],{"class":196,"line":939},[194,1761,1762],{},"    Pcreg Reg20 (clk,rst,switch[19],wdata,array_reg[19]);\n",[194,1764,1765],{"class":196,"line":945},[194,1766,1767],{},"    Pcreg Reg21 (clk,rst,switch[20],wdata,array_reg[20]);\n",[194,1769,1770],{"class":196,"line":951},[194,1771,1772],{},"    Pcreg Reg22 (clk,rst,switch[21],wdata,array_reg[21]);\n",[194,1774,1775],{"class":196,"line":957},[194,1776,1777],{},"    Pcreg Reg23 (clk,rst,switch[22],wdata,array_reg[22]);\n",[194,1779,1780],{"class":196,"line":963},[194,1781,1782],{},"    Pcreg Reg24 (clk,rst,switch[23],wdata,array_reg[23]);\n",[194,1784,1785],{"class":196,"line":969},[194,1786,1787],{},"    Pcreg Reg25 (clk,rst,switch[24],wdata,array_reg[24]);\n",[194,1789,1790],{"class":196,"line":974},[194,1791,1792],{},"    Pcreg Reg26 (clk,rst,switch[25],wdata,array_reg[25]);\n",[194,1794,1795],{"class":196,"line":980},[194,1796,1797],{},"    Pcreg Reg27 (clk,rst,switch[26],wdata,array_reg[26]);\n",[194,1799,1800],{"class":196,"line":986},[194,1801,1802],{},"    Pcreg Reg28 (clk,rst,switch[27],wdata,array_reg[27]);\n",[194,1804,1805],{"class":196,"line":991},[194,1806,1807],{},"    Pcreg Reg29 (clk,rst,switch[28],wdata,array_reg[28]);\n",[194,1809,1810],{"class":196,"line":997},[194,1811,1812],{},"    Pcreg Reg30 (clk,rst,switch[29],wdata,array_reg[29]);\n",[194,1814,1815],{"class":196,"line":1003},[194,1816,1817],{},"    Pcreg Reg31 (clk,rst,switch[30],wdata,array_reg[30]);\n",[194,1819,1820],{"class":196,"line":1009},[194,1821,1822],{},"    Pcreg Reg32 (clk,rst,switch[31],wdata,array_reg[31]);\n",[194,1824,1825],{"class":196,"line":1015},[194,1826,1827],{},"    assign rdata1 = array_reg[raddr1];\n",[194,1829,1830],{"class":196,"line":1021},[194,1831,1832],{},"    assign rdata2 = array_reg[raddr2];\n",[194,1834,1835],{"class":196,"line":1027},[194,1836,284],{},[194,1838,1839],{"class":196,"line":1033},[194,1840,537],{"emptyLinePlaceholder":536},[194,1842,1843],{"class":196,"line":1038},[194,1844,1845],{},"module Decoder(\n",[194,1847,1848],{"class":196,"line":1362},[194,1849,1850],{},"    input [4:0] iData,      \n",[194,1852,1853],{"class":196,"line":1368},[194,1854,1855],{},"    input  iEna,            \n",[194,1857,1858],{"class":196,"line":1373},[194,1859,1860],{},"    output [31:0] oData      \n",[194,1862,1863],{"class":196,"line":1379},[194,1864,1865],{},"    );        \n",[194,1867,1868],{"class":196,"line":1385},[194,1869,1870],{},"    assign oData=(iEna==1)?(32'b00000000000000000000000000000001\u003C\u003CiData):32'bx;\n",[194,1872,1873],{"class":196,"line":1390},[194,1874,284],{},[194,1876,1877],{"class":196,"line":1396},[194,1878,537],{"emptyLinePlaceholder":536},[194,1880,1881],{"class":196,"line":1402},[194,1882,1883],{},"module Pcreg(\n",[194,1885,1886],{"class":196,"line":1407},[194,1887,700],{},[194,1889,1890],{"class":196,"line":1413},[194,1891,705],{},[194,1893,1894],{"class":196,"line":1419},[194,1895,710],{},[194,1897,1898],{"class":196,"line":1424},[194,1899,715],{},[194,1901,1902],{"class":196,"line":1430},[194,1903,720],{},[194,1905,1906],{"class":196,"line":1436},[194,1907,725],{},[194,1909,1910],{"class":196,"line":1441},[194,1911,236],{},[194,1913,1914],{"class":196,"line":1447},[194,1915,977],{},[194,1917,1918],{"class":196,"line":1453},[194,1919,1920],{},"    D_FF d0 (clk,data_in[0],ena,rst,data_out[0]);\n",[194,1922,1923],{"class":196,"line":1458},[194,1924,1925],{},"    D_FF d1 (clk,data_in[1],ena,rst,data_out[1]);\n",[194,1927,1928],{"class":196,"line":1464},[194,1929,1930],{},"    D_FF d2 (clk,data_in[2],ena,rst,data_out[2]);\n",[194,1932,1933],{"class":196,"line":1470},[194,1934,1935],{},"    D_FF d3 (clk,data_in[3],ena,rst,data_out[3]);\n",[194,1937,1938],{"class":196,"line":1475},[194,1939,1940],{},"    D_FF d4 (clk,data_in[4],ena,rst,data_out[4]);\n",[194,1942,1943],{"class":196,"line":1481},[194,1944,1945],{},"    D_FF d5 (clk,data_in[5],ena,rst,data_out[5]);\n",[194,1947,1948],{"class":196,"line":1486},[194,1949,1950],{},"    D_FF d6 (clk,data_in[6],ena,rst,data_out[6]);\n",[194,1952,1953],{"class":196,"line":1491},[194,1954,1955],{},"    D_FF d7 (clk,data_in[7],ena,rst,data_out[7]);\n",[194,1957,1958],{"class":196,"line":1497},[194,1959,1960],{},"    D_FF d8 (clk,data_in[8],ena,rst,data_out[8]);\n",[194,1962,1963],{"class":196,"line":1503},[194,1964,1965],{},"    D_FF d9 (clk,data_in[9],ena,rst,data_out[9]);\n",[194,1967,1968],{"class":196,"line":1509},[194,1969,1970],{},"    D_FF d10 (clk,data_in[10],ena,rst,data_out[10]);\n",[194,1972,1973],{"class":196,"line":1515},[194,1974,1975],{},"    D_FF d11 (clk,data_in[11],ena,rst,data_out[11]);\n",[194,1977,1978],{"class":196,"line":1521},[194,1979,1980],{},"    D_FF d12 (clk,data_in[12],ena,rst,data_out[12]);\n",[194,1982,1984],{"class":196,"line":1983},94,[194,1985,1986],{},"    D_FF d13 (clk,data_in[13],ena,rst,data_out[13]);\n",[194,1988,1990],{"class":196,"line":1989},95,[194,1991,1992],{},"    D_FF d14 (clk,data_in[14],ena,rst,data_out[14]);\n",[194,1994,1996],{"class":196,"line":1995},96,[194,1997,1998],{},"    D_FF d15 (clk,data_in[15],ena,rst,data_out[15]);\n",[194,2000,2002],{"class":196,"line":2001},97,[194,2003,2004],{},"    D_FF d16 (clk,data_in[16],ena,rst,data_out[16]);\n",[194,2006,2008],{"class":196,"line":2007},98,[194,2009,2010],{},"    D_FF d17 (clk,data_in[17],ena,rst,data_out[17]);\n",[194,2012,2014],{"class":196,"line":2013},99,[194,2015,2016],{},"    D_FF d18 (clk,data_in[18],ena,rst,data_out[18]);\n",[194,2018,2020],{"class":196,"line":2019},100,[194,2021,2022],{},"    D_FF d19 (clk,data_in[19],ena,rst,data_out[19]);\n",[194,2024,2026],{"class":196,"line":2025},101,[194,2027,2028],{},"    D_FF d20 (clk,data_in[20],ena,rst,data_out[20]);\n",[194,2030,2032],{"class":196,"line":2031},102,[194,2033,2034],{},"    D_FF d21 (clk,data_in[21],ena,rst,data_out[21]);\n",[194,2036,2038],{"class":196,"line":2037},103,[194,2039,2040],{},"    D_FF d22 (clk,data_in[22],ena,rst,data_out[22]);\n",[194,2042,2044],{"class":196,"line":2043},104,[194,2045,2046],{},"    D_FF d23 (clk,data_in[23],ena,rst,data_out[23]);\n",[194,2048,2050],{"class":196,"line":2049},105,[194,2051,2052],{},"    D_FF d24 (clk,data_in[24],ena,rst,data_out[24]);\n",[194,2054,2056],{"class":196,"line":2055},106,[194,2057,2058],{},"    D_FF d25 (clk,data_in[25],ena,rst,data_out[25]);\n",[194,2060,2062],{"class":196,"line":2061},107,[194,2063,2064],{},"    D_FF d26 (clk,data_in[26],ena,rst,data_out[26]);\n",[194,2066,2068],{"class":196,"line":2067},108,[194,2069,2070],{},"    D_FF d27 (clk,data_in[27],ena,rst,data_out[27]);\n",[194,2072,2074],{"class":196,"line":2073},109,[194,2075,2076],{},"    D_FF d28 (clk,data_in[28],ena,rst,data_out[28]);\n",[194,2078,2080],{"class":196,"line":2079},110,[194,2081,2082],{},"    D_FF d29 (clk,data_in[29],ena,rst,data_out[29]);\n",[194,2084,2086],{"class":196,"line":2085},111,[194,2087,2088],{},"    D_FF d30 (clk,data_in[30],ena,rst,data_out[30]);\n",[194,2090,2092],{"class":196,"line":2091},112,[194,2093,2094],{},"    D_FF d31 (clk,data_in[31],ena,rst,data_out[31]);   \n",[194,2096,2098],{"class":196,"line":2097},113,[194,2099,284],{},[194,2101,2103],{"class":196,"line":2102},114,[194,2104,537],{"emptyLinePlaceholder":536},[194,2106,2108],{"class":196,"line":2107},115,[194,2109,2110],{},"module D_FF(\n",[194,2112,2114],{"class":196,"line":2113},116,[194,2115,942],{},[194,2117,2119],{"class":196,"line":2118},117,[194,2120,948],{},[194,2122,2124],{"class":196,"line":2123},118,[194,2125,954],{},[194,2127,2129],{"class":196,"line":2128},119,[194,2130,960],{},[194,2132,2134],{"class":196,"line":2133},120,[194,2135,2136],{},"    output reg Q1   \u002F\u002F输出信号 Q1\n",[194,2138,2140],{"class":196,"line":2139},121,[194,2141,236],{},[194,2143,2145],{"class":196,"line":2144},122,[194,2146,977],{},[194,2148,2150],{"class":196,"line":2149},123,[194,2151,2152],{},"    \u002F\u002F 2020\u002F03\u002F29 有小伙伴指出这里可能有问题, negedge CLK, 请以仿真结果为准(博主无法进行仿真了)\n",[194,2154,2156],{"class":196,"line":2155},124,[194,2157,2158],{},"    always @(posedge RST_n or posedge CLK)\n",[194,2160,2162],{"class":196,"line":2161},125,[194,2163,248],{},[194,2165,2167],{"class":196,"line":2166},126,[194,2168,994],{},[194,2170,2172],{"class":196,"line":2171},127,[194,2173,2174],{},"        Q1 = 0;\n",[194,2176,2178],{"class":196,"line":2177},128,[194,2179,1006],{},[194,2181,2183],{"class":196,"line":2182},129,[194,2184,2185],{},"      begin\n",[194,2187,2189],{"class":196,"line":2188},130,[194,2190,2191],{},"      if(ENA==1)\n",[194,2193,2195],{"class":196,"line":2194},131,[194,2196,2197],{},"        Q1 = D;\n",[194,2199,2201],{"class":196,"line":2200},132,[194,2202,2203],{},"      end\n",[194,2205,2207],{"class":196,"line":2206},133,[194,2208,382],{},[194,2210,2212],{"class":196,"line":2211},134,[194,2213,284],{},[157,2215,2216],{},[160,2217,2218],{},"II",[184,2220,2222],{"className":186,"code":2221,"language":188,"meta":189,"style":189},"`timescale 1ns \u002F 1ns\nmodule II(\n    input [3:0] a,\n    input [25:0] b,\n    output [31:0] r\n    );\n    assign r = {a, b\u003C\u003C2};\nendmodule\n",[191,2223,2224,2228,2233,2238,2243,2247,2251,2256],{"__ignoreMap":189},[194,2225,2226],{"class":196,"line":197},[194,2227,200],{},[194,2229,2230],{"class":196,"line":203},[194,2231,2232],{},"module II(\n",[194,2234,2235],{"class":196,"line":209},[194,2236,2237],{},"    input [3:0] a,\n",[194,2239,2240],{"class":196,"line":215},[194,2241,2242],{},"    input [25:0] b,\n",[194,2244,2245],{"class":196,"line":221},[194,2246,610],{},[194,2248,2249],{"class":196,"line":227},[194,2250,236],{},[194,2252,2253],{"class":196,"line":233},[194,2254,2255],{},"    assign r = {a, b\u003C\u003C2};\n",[194,2257,2258],{"class":196,"line":239},[194,2259,284],{},[2261,2262,2263],"style",{},"html .light .shiki span {color: var(--shiki-light);background: var(--shiki-light-bg);font-style: var(--shiki-light-font-style);font-weight: var(--shiki-light-font-weight);text-decoration: var(--shiki-light-text-decoration);}html.light .shiki span {color: var(--shiki-light);background: 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