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server的基本使用","\u002Fgolang\u002Fgopls_mcp_usages","1.golang\u002F2.gopls_mcp_usages",{"title":16,"path":17,"stem":18},"实践-(一)创建简单的http服务器","\u002Fgolang\u002Fgo_http_simple_server","1.golang\u002F3.go_http_simple_server",{"title":20,"path":21,"stem":22},"wails入门系列(一)环境安装与demo","\u002Fgolang\u002Fwails_start","1.golang\u002F4.wails_start",{"title":24,"path":25,"stem":26},"wails入门系列(二)无边框应用的菜单栏以及窗口拖拽","\u002Fgolang\u002Fwails_frameless","1.golang\u002F5.wails_frameless",{"title":28,"path":29,"stem":30},"go\u002Fredis-redis中大数字自动转换成指数形式的处理","\u002Fgolang\u002Fredis_big_num","1.golang\u002F6.redis_big_num",{"title":32,"path":33,"stem":34},"go\u002F方法记录-局部坐标与世界坐标间的相互转换(位置\u002F方向)","\u002Fgolang\u002Fworld_local_transform","1.golang\u002F7.world_local_transform",false,{"title":37,"icon":35,"path":38,"stem":39,"children":40,"page":35},"瞎折腾","\u002Ftinkering","2.tinkering",[41,45,49],{"title":42,"path":43,"stem":44},"mi50显卡ubuntu运行大模型开坑(一)显卡准备以及驱动安装","\u002Ftinkering\u002Fmi50_gpu_llm_1","2.tinkering\u002F1.mi50_gpu_llm_1",{"title":46,"path":47,"stem":48},"mi50显卡ubuntu运行大模型开坑(二)使用llama.cpp部署Qwen3系列","\u002Ftinkering\u002Fmi50_gpu_llm_2","2.tinkering\u002F2.mi50_gpu_llm_2",{"title":50,"path":51,"stem":52},"mi50显卡ubuntu运行大模型开坑(三)安装风扇并且控制转速","\u002Ftinkering\u002Fmi50_gpu_llm_3","2.tinkering\u002F3.mi50_gpu_llm_3",{"title":54,"icon":35,"path":55,"stem":56,"children":57,"page":35},"LLM","\u002Fllm","3.llm",[58,62,66,70,74,78,82],{"title":59,"path":60,"stem":61},"langchain入门-安装以及初次使用(deepseek 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agent-zero初步搭建与使用","\u002Fllm\u002Fagent_zero_start","3.llm\u002F07.agent_zero_start",{"title":87,"icon":35,"path":88,"stem":89,"children":90,"page":35},"Verilog","\u002Fverilog","4.verilog",[91,95,99,103,107,111,115,119,123,127],{"title":92,"path":93,"stem":94},"31条指令单周期cpu设计(Verilog)-(一)相关软件","\u002Fverilog\u002Fmips1","4.verilog\u002F01.mips1",{"title":96,"path":97,"stem":98},"31条指令单周期cpu设计(Verilog)-(二)总体设计","\u002Fverilog\u002Fmips2","4.verilog\u002F02.mips2",{"title":100,"path":101,"stem":102},"31条指令单周期cpu设计(Verilog)-(三)指令分析","\u002Fverilog\u002Fmips3","4.verilog\u002F03.mips3",{"title":104,"path":105,"stem":106},"31条指令单周期cpu设计(Verilog)-(四)数据输入输出关系表","\u002Fverilog\u002Fmips4","4.verilog\u002F04.mips4",{"title":108,"path":109,"stem":110},"31条指令单周期cpu设计(Verilog)-(五)整体数据通路图设计","\u002Fverilog\u002Fmips5","4.verilog\u002F05.mips5",{"title":112,"path":113,"stem":114},"31条指令单周期cpu设计(Verilog)-(六)指令操作时间表设计","\u002Fverilog\u002Fmips6","4.verilog\u002F06.mips6",{"title":116,"path":117,"stem":118},"31条指令单周期cpu设计(Verilog)-(七)整体代码结构","\u002Fverilog\u002Fmips7","4.verilog\u002F07.mips7",{"title":120,"path":121,"stem":122},"31条指令单周期cpu设计(Verilog)-(八)上代码→指令译码以及控制器","\u002Fverilog\u002Fmips8","4.verilog\u002F08.mips8",{"title":124,"path":125,"stem":126},"31条指令单周期cpu设计(Verilog)-(九)上代码→基础模块实现","\u002Fverilog\u002Fmips9","4.verilog\u002F09.mips9",{"title":128,"path":129,"stem":130},"31条指令单周期cpu设计(Verilog)-(十)上代码→顶层模块设计&总结","\u002Fverilog\u002Fmips10","4.verilog\u002F10.mips10",{"title":132,"icon":35,"path":133,"stem":134,"children":135,"page":35},"Rust","\u002Frust","5.rust",[136,140],{"title":137,"path":138,"stem":139},"egui(一)从编译运行template开始","\u002Frust\u002Fegui1","5.rust\u002F01.egui1",{"title":141,"path":142,"stem":143},"egui(二)看看template的main函数：日志输出以及eframe run_native","\u002Frust\u002Fegui2","5.rust\u002F02.egui2",{"id":145,"title":120,"body":146,"description":859,"extension":860,"links":861,"meta":862,"navigation":864,"path":121,"seo":865,"stem":122,"__hash__":868},"docs\u002F4.verilog\u002F08.mips8.md",{"type":147,"value":148,"toc":854},"minimark",[149,153,172,175,475,478,850],[150,151,152],"h2",{"id":152},"说在前面",[154,155,156],"blockquote",{},[157,158,159,163,166,169],"ul",{},[160,161,162],"li",{},"开发环境：Vivado",[160,164,165],{},"语言：Verilog",[160,167,168],{},"cpu框架：Mips",[160,170,171],{},"控制器：组合逻辑",[150,173,174],{"id":174},"指令译码器",[157,176,177,185],{},[160,178,179,180],{},"我们需要根据一条32位的指令的结构确定是哪一条指令\n",[181,182],"img",{"alt":183,"src":184},"",".\u002Fverilog\u002F46.webp",[160,186,187,188],{},"可以根据操作码(op)以及功能码（func），使用case语句确定（下述代码中case语句顺序与上表相同）\n",[189,190,194],"pre",{"className":191,"code":192,"language":193,"meta":183,"style":183},"language-verilog shiki shiki-themes material-theme-lighter material-theme material-theme-palenight","`timescale 1ns \u002F 1ns\nmodule instr_dec(\n  input [31:0] instr_code,\n  output reg [31:0] i\n  );\n  wire [11:0] t;\n  assign t = {instr_code[31:26],instr_code[5:0]};\n  always @ (*)\n  begin\n      casez(t)\n          12'b000000100000 :i = 32'b00000000000000000000000000000001;\n          12'b000000100001 :i = 32'b00000000000000000000000000000010;\n          12'b000000100010 :i = 32'b00000000000000000000000000000100;\n          12'b000000100011 :i = 32'b00000000000000000000000000001000;\n          12'b000000100100 :i = 32'b00000000000000000000000000010000;\n          12'b000000100101 :i = 32'b00000000000000000000000000100000;\n          12'b000000100110 :i = 32'b00000000000000000000000001000000;\n          12'b000000100111 :i = 32'b00000000000000000000000010000000;\n          12'b000000101010 :i = 32'b00000000000000000000000100000000;\n          12'b000000101011 :i = 32'b00000000000000000000001000000000;\n          12'b000000000000 :i = 32'b00000000000000000000010000000000;\n          12'b000000000010 :i = 32'b00000000000000000000100000000000;\n          12'b000000000011 :i = 32'b00000000000000000001000000000000;\n          12'b000000000100 :i = 32'b00000000000000000010000000000000;\n          12'b000000000110 :i = 32'b00000000000000000100000000000000;\n          12'b000000000111 :i = 32'b00000000000000001000000000000000;\n          12'b000000001000 :i = 32'b00000000000000010000000000000000;\n          12'b001000?????? :i = 32'b00000000000000100000000000000000;\n          12'b001001?????? :i = 32'b00000000000001000000000000000000;\n          12'b001100?????? :i = 32'b00000000000010000000000000000000;\n          12'b001101?????? :i = 32'b00000000000100000000000000000000;\n          12'b001110?????? :i = 32'b00000000001000000000000000000000;\n          12'b100011?????? :i = 32'b00000000010000000000000000000000;\n          12'b101011?????? :i = 32'b00000000100000000000000000000000;\n          12'b000100?????? :i = 32'b00000001000000000000000000000000;\n          12'b000101?????? :i = 32'b00000010000000000000000000000000;\n          12'b001010?????? :i = 32'b00000100000000000000000000000000;\n          12'b001011?????? :i = 32'b00001000000000000000000000000000;\n          12'b001111?????? :i = 32'b00010000000000000000000000000000;\n          12'b000010?????? :i = 32'b00100000000000000000000000000000;\n          12'b000011?????? :i = 32'b01000000000000000000000000000000;\n          default:          i = 32'bx;\n      endcase\n  end\n  \nendmodule\n","verilog",[195,196,197,205,211,217,223,229,235,241,247,253,259,265,271,277,283,289,295,301,307,313,319,325,331,337,343,349,355,361,367,373,379,385,391,397,403,409,415,421,427,433,439,445,451,457,463,469],"code",{"__ignoreMap":183},[198,199,202],"span",{"class":200,"line":201},"line",1,[198,203,204],{},"`timescale 1ns \u002F 1ns\n",[198,206,208],{"class":200,"line":207},2,[198,209,210],{},"module instr_dec(\n",[198,212,214],{"class":200,"line":213},3,[198,215,216],{},"  input [31:0] instr_code,\n",[198,218,220],{"class":200,"line":219},4,[198,221,222],{},"  output reg [31:0] i\n",[198,224,226],{"class":200,"line":225},5,[198,227,228],{},"  );\n",[198,230,232],{"class":200,"line":231},6,[198,233,234],{},"  wire [11:0] t;\n",[198,236,238],{"class":200,"line":237},7,[198,239,240],{},"  assign t = {instr_code[31:26],instr_code[5:0]};\n",[198,242,244],{"class":200,"line":243},8,[198,245,246],{},"  always @ (*)\n",[198,248,250],{"class":200,"line":249},9,[198,251,252],{},"  begin\n",[198,254,256],{"class":200,"line":255},10,[198,257,258],{},"      casez(t)\n",[198,260,262],{"class":200,"line":261},11,[198,263,264],{},"          12'b000000100000 :i = 32'b00000000000000000000000000000001;\n",[198,266,268],{"class":200,"line":267},12,[198,269,270],{},"          12'b000000100001 :i = 32'b00000000000000000000000000000010;\n",[198,272,274],{"class":200,"line":273},13,[198,275,276],{},"          12'b000000100010 :i = 32'b00000000000000000000000000000100;\n",[198,278,280],{"class":200,"line":279},14,[198,281,282],{},"          12'b000000100011 :i = 32'b00000000000000000000000000001000;\n",[198,284,286],{"class":200,"line":285},15,[198,287,288],{},"          12'b000000100100 :i = 32'b00000000000000000000000000010000;\n",[198,290,292],{"class":200,"line":291},16,[198,293,294],{},"          12'b000000100101 :i = 32'b00000000000000000000000000100000;\n",[198,296,298],{"class":200,"line":297},17,[198,299,300],{},"          12'b000000100110 :i = 32'b00000000000000000000000001000000;\n",[198,302,304],{"class":200,"line":303},18,[198,305,306],{},"          12'b000000100111 :i = 32'b00000000000000000000000010000000;\n",[198,308,310],{"class":200,"line":309},19,[198,311,312],{},"          12'b000000101010 :i = 32'b00000000000000000000000100000000;\n",[198,314,316],{"class":200,"line":315},20,[198,317,318],{},"          12'b000000101011 :i = 32'b00000000000000000000001000000000;\n",[198,320,322],{"class":200,"line":321},21,[198,323,324],{},"          12'b000000000000 :i = 32'b00000000000000000000010000000000;\n",[198,326,328],{"class":200,"line":327},22,[198,329,330],{},"          12'b000000000010 :i = 32'b00000000000000000000100000000000;\n",[198,332,334],{"class":200,"line":333},23,[198,335,336],{},"          12'b000000000011 :i = 32'b00000000000000000001000000000000;\n",[198,338,340],{"class":200,"line":339},24,[198,341,342],{},"          12'b000000000100 :i = 32'b00000000000000000010000000000000;\n",[198,344,346],{"class":200,"line":345},25,[198,347,348],{},"          12'b000000000110 :i = 32'b00000000000000000100000000000000;\n",[198,350,352],{"class":200,"line":351},26,[198,353,354],{},"          12'b000000000111 :i = 32'b00000000000000001000000000000000;\n",[198,356,358],{"class":200,"line":357},27,[198,359,360],{},"          12'b000000001000 :i = 32'b00000000000000010000000000000000;\n",[198,362,364],{"class":200,"line":363},28,[198,365,366],{},"          12'b001000?????? :i = 32'b00000000000000100000000000000000;\n",[198,368,370],{"class":200,"line":369},29,[198,371,372],{},"          12'b001001?????? :i = 32'b00000000000001000000000000000000;\n",[198,374,376],{"class":200,"line":375},30,[198,377,378],{},"          12'b001100?????? :i = 32'b00000000000010000000000000000000;\n",[198,380,382],{"class":200,"line":381},31,[198,383,384],{},"          12'b001101?????? :i = 32'b00000000000100000000000000000000;\n",[198,386,388],{"class":200,"line":387},32,[198,389,390],{},"          12'b001110?????? :i = 32'b00000000001000000000000000000000;\n",[198,392,394],{"class":200,"line":393},33,[198,395,396],{},"          12'b100011?????? :i = 32'b00000000010000000000000000000000;\n",[198,398,400],{"class":200,"line":399},34,[198,401,402],{},"          12'b101011?????? :i = 32'b00000000100000000000000000000000;\n",[198,404,406],{"class":200,"line":405},35,[198,407,408],{},"          12'b000100?????? :i = 32'b00000001000000000000000000000000;\n",[198,410,412],{"class":200,"line":411},36,[198,413,414],{},"          12'b000101?????? :i = 32'b00000010000000000000000000000000;\n",[198,416,418],{"class":200,"line":417},37,[198,419,420],{},"          12'b001010?????? :i = 32'b00000100000000000000000000000000;\n",[198,422,424],{"class":200,"line":423},38,[198,425,426],{},"          12'b001011?????? :i = 32'b00001000000000000000000000000000;\n",[198,428,430],{"class":200,"line":429},39,[198,431,432],{},"          12'b001111?????? :i = 32'b00010000000000000000000000000000;\n",[198,434,436],{"class":200,"line":435},40,[198,437,438],{},"          12'b000010?????? :i = 32'b00100000000000000000000000000000;\n",[198,440,442],{"class":200,"line":441},41,[198,443,444],{},"          12'b000011?????? :i = 32'b01000000000000000000000000000000;\n",[198,446,448],{"class":200,"line":447},42,[198,449,450],{},"          default:          i = 32'bx;\n",[198,452,454],{"class":200,"line":453},43,[198,455,456],{},"      endcase\n",[198,458,460],{"class":200,"line":459},44,[198,461,462],{},"  end\n",[198,464,466],{"class":200,"line":465},45,[198,467,468],{},"  \n",[198,470,472],{"class":200,"line":471},46,[198,473,474],{},"endmodule\n",[150,476,477],{"id":477},"控制器",[157,479,480,488,497],{},[160,481,482,483],{},"输入为",[198,484,487],{"className":485},[486],"text-error","指令译码器的输出",[160,489,490,491,496],{},"输出为",[198,492,495],{"className":493},[494],"text-success","控制信号","，依据指令操作时间表进行设计",[160,498,499,500,617],{},"逻辑表达式",[189,501,505],{"className":502,"code":503,"language":504,"meta":183,"style":183},"language-per shiki shiki-themes material-theme-lighter material-theme material-theme-palenight","PC_CLK = 1\nIM_R = 1\nRsc4-0 = IM25-21\nRtc4-0 = IM20-16\nM1 = ~(jr + j + jal)\nM2 = beq + bne\nM3 = jr\nM4 = sllv + srlv + srav\nM5 = addi + addiu + andi + ori + xori + lw + sw + slti + sltiu + lui\nM6 = jal\nM7 = lw\nM9 = ~(sll + srl + sra + sllv + srlv + srav)\nM10 = addi + addiu + andi + ori + xori + lw + sw + slti + sltiu + lui\nA0 = sub + subu + or + nor + slt + srl + srlv + ori + beq + bne + slti\nA1 = add + sub + xor + nor + slt + sltu + sll + sllv + addi + xori + lw + sw +beq +bne + slti +sltiu\nA2 = and + or + xor + nor + sll + srl + sra + sllv + srlv +srav + andi + ori + xori\nA3 = slt + sltu + sll + srl + sra +sllv + srlv + srav + slti + sltiu + lui\nRF_W = ~(jr + sw + beq + bne + j)\nRF_CLK = ~(jr + sw + beq + bne + j) clk\nDM_w = sw\nDM_r = lw\nDM_cs = lw +sw\n","per",[195,506,507,512,517,522,527,532,537,542,547,552,557,562,567,572,577,582,587,592,597,602,607,612],{"__ignoreMap":183},[198,508,509],{"class":200,"line":201},[198,510,511],{},"PC_CLK = 1\n",[198,513,514],{"class":200,"line":207},[198,515,516],{},"IM_R = 1\n",[198,518,519],{"class":200,"line":213},[198,520,521],{},"Rsc4-0 = IM25-21\n",[198,523,524],{"class":200,"line":219},[198,525,526],{},"Rtc4-0 = IM20-16\n",[198,528,529],{"class":200,"line":225},[198,530,531],{},"M1 = ~(jr + j + jal)\n",[198,533,534],{"class":200,"line":231},[198,535,536],{},"M2 = beq + bne\n",[198,538,539],{"class":200,"line":237},[198,540,541],{},"M3 = jr\n",[198,543,544],{"class":200,"line":243},[198,545,546],{},"M4 = sllv + srlv + srav\n",[198,548,549],{"class":200,"line":249},[198,550,551],{},"M5 = addi + addiu + andi + ori + xori + lw + sw + slti + sltiu + lui\n",[198,553,554],{"class":200,"line":255},[198,555,556],{},"M6 = jal\n",[198,558,559],{"class":200,"line":261},[198,560,561],{},"M7 = lw\n",[198,563,564],{"class":200,"line":267},[198,565,566],{},"M9 = ~(sll + srl + sra + sllv + srlv + srav)\n",[198,568,569],{"class":200,"line":273},[198,570,571],{},"M10 = addi + addiu + andi + ori + xori + lw + sw + slti + sltiu + lui\n",[198,573,574],{"class":200,"line":279},[198,575,576],{},"A0 = sub + subu + or + nor + slt + srl + srlv + ori + beq + bne + slti\n",[198,578,579],{"class":200,"line":285},[198,580,581],{},"A1 = add + sub + xor + nor + slt + sltu + sll + sllv + addi + xori + lw + sw +beq +bne + slti +sltiu\n",[198,583,584],{"class":200,"line":291},[198,585,586],{},"A2 = and + or + xor + nor + sll + srl + sra + sllv + srlv +srav + andi + ori + xori\n",[198,588,589],{"class":200,"line":297},[198,590,591],{},"A3 = slt + sltu + sll + srl + sra +sllv + srlv + srav + slti + sltiu + lui\n",[198,593,594],{"class":200,"line":303},[198,595,596],{},"RF_W = ~(jr + sw + beq + bne + j)\n",[198,598,599],{"class":200,"line":309},[198,600,601],{},"RF_CLK = ~(jr + sw + beq + bne + j) clk\n",[198,603,604],{"class":200,"line":315},[198,605,606],{},"DM_w = sw\n",[198,608,609],{"class":200,"line":321},[198,610,611],{},"DM_r = lw\n",[198,613,614],{"class":200,"line":327},[198,615,616],{},"DM_cs = lw +sw\n",[189,618,620],{"className":191,"code":619,"language":193,"meta":183,"style":183},"`timescale 1ns \u002F 1ns\nmodule operation(\n    input clk,\n    input z,\n    input [31:0] i,\n    output PC_CLK,    \n    output IM_R,     \n    output M1,       \n    output M2,        \n    output M3,        \n    output M4,        \n    output M5,        \n    output M6,       \n    output M7,       \n    output M9,      \n    output M10,      \n    output [3:0] ALUC,\n    output RF_W,     \n    output RF_CLK,   \n    output DM_w,   \n    output DM_r,     \n    output DM_cs,\n    output C_EXT16\n    );\n    assign PC_CLK = clk;\n    assign IM_R = 1;\n    assign M1 = ~(i[16] | i[29] | i[30]);\n    assign M2 = ( i[24] & z) | (i[25] & ~z);\n    assign M3 = i[16];\n    assign M4 = i[13] | i[14] | i[15];\n    assign M5 = i[17] | i[18] | i[19] | i[20] | i[21] | i[22] | i[23] | i[26] | i[27] | i[28];\n    assign M6 = i[30];\n    assign M7 = i[22];\n    assign M9 = ~(i[10] | i[11] | i[12] | i[13] | i[14] | i[15]);\n    assign M10 = i[17] | i[18] | i[19] | i[20] | i[21] | i[22] | i[23] | i[26] | i[27] | i[28];\n    assign ALUC[0] = i[2] | i[3] | i[5] | i[7] | i[8] | i[11] | i[14] | i[20] | i[24] | i[25] | i[26];\n    assign ALUC[1] = i[0] | i[2] | i[6] | i[7] | i[8] | i[9] | i[10] | i[13] | i[17] | i[21] | i[22] | i[23] | i[24] | i[25] | i[26] | i[27];\n    assign ALUC[2] = i[4] | i[5] | i[6] | i[7] | i[10] | i[11] | i[12] | i[13] | i[14] | i[15] | i[19] | i[20] | i[21];\n    assign ALUC[3] = i[8] | i[9] | i[10] | i[11] | i[12] | i[13] | i[14] | i[15] | i[26] | i[27] | i[28];\n    assign RF_W = ~(i[16] | i[23] | i[24] | i[25] | i[29]);\n    assign RF_CLK = ~clk;\n    assign DM_w = i[23];\n    assign DM_r = i[22];\n    assign DM_cs = i[22] | i[23];\n    assign C_EXT16 = ~(i[19] | i[20] | i[21]);\nendmodule\n",[195,621,622,626,631,636,641,646,651,656,661,666,671,676,681,686,691,696,701,706,711,716,721,726,731,736,741,746,751,756,761,766,771,776,781,786,791,796,801,806,811,816,821,826,831,836,841,846],{"__ignoreMap":183},[198,623,624],{"class":200,"line":201},[198,625,204],{},[198,627,628],{"class":200,"line":207},[198,629,630],{},"module operation(\n",[198,632,633],{"class":200,"line":213},[198,634,635],{},"    input clk,\n",[198,637,638],{"class":200,"line":219},[198,639,640],{},"    input z,\n",[198,642,643],{"class":200,"line":225},[198,644,645],{},"    input [31:0] i,\n",[198,647,648],{"class":200,"line":231},[198,649,650],{},"    output PC_CLK,    \n",[198,652,653],{"class":200,"line":237},[198,654,655],{},"    output IM_R,     \n",[198,657,658],{"class":200,"line":243},[198,659,660],{},"    output M1,       \n",[198,662,663],{"class":200,"line":249},[198,664,665],{},"    output M2,        \n",[198,667,668],{"class":200,"line":255},[198,669,670],{},"    output M3,        \n",[198,672,673],{"class":200,"line":261},[198,674,675],{},"    output M4,        \n",[198,677,678],{"class":200,"line":267},[198,679,680],{},"    output M5,        \n",[198,682,683],{"class":200,"line":273},[198,684,685],{},"    output M6,       \n",[198,687,688],{"class":200,"line":279},[198,689,690],{},"    output M7,       \n",[198,692,693],{"class":200,"line":285},[198,694,695],{},"    output M9,      \n",[198,697,698],{"class":200,"line":291},[198,699,700],{},"    output M10,      \n",[198,702,703],{"class":200,"line":297},[198,704,705],{},"    output [3:0] ALUC,\n",[198,707,708],{"class":200,"line":303},[198,709,710],{},"    output RF_W,     \n",[198,712,713],{"class":200,"line":309},[198,714,715],{},"    output RF_CLK,   \n",[198,717,718],{"class":200,"line":315},[198,719,720],{},"    output DM_w,   \n",[198,722,723],{"class":200,"line":321},[198,724,725],{},"    output DM_r,     \n",[198,727,728],{"class":200,"line":327},[198,729,730],{},"    output DM_cs,\n",[198,732,733],{"class":200,"line":333},[198,734,735],{},"    output C_EXT16\n",[198,737,738],{"class":200,"line":339},[198,739,740],{},"    );\n",[198,742,743],{"class":200,"line":345},[198,744,745],{},"    assign PC_CLK = clk;\n",[198,747,748],{"class":200,"line":351},[198,749,750],{},"    assign IM_R = 1;\n",[198,752,753],{"class":200,"line":357},[198,754,755],{},"    assign M1 = ~(i[16] | i[29] | i[30]);\n",[198,757,758],{"class":200,"line":363},[198,759,760],{},"    assign M2 = ( i[24] & z) | (i[25] & ~z);\n",[198,762,763],{"class":200,"line":369},[198,764,765],{},"    assign M3 = i[16];\n",[198,767,768],{"class":200,"line":375},[198,769,770],{},"    assign M4 = i[13] | i[14] | i[15];\n",[198,772,773],{"class":200,"line":381},[198,774,775],{},"    assign M5 = i[17] | i[18] | i[19] | i[20] | i[21] | i[22] | i[23] | i[26] | i[27] | i[28];\n",[198,777,778],{"class":200,"line":387},[198,779,780],{},"    assign M6 = i[30];\n",[198,782,783],{"class":200,"line":393},[198,784,785],{},"    assign M7 = i[22];\n",[198,787,788],{"class":200,"line":399},[198,789,790],{},"    assign M9 = ~(i[10] | i[11] | i[12] | i[13] | i[14] | i[15]);\n",[198,792,793],{"class":200,"line":405},[198,794,795],{},"    assign M10 = i[17] | i[18] | i[19] | i[20] | i[21] | i[22] | i[23] | i[26] | i[27] | i[28];\n",[198,797,798],{"class":200,"line":411},[198,799,800],{},"    assign ALUC[0] = i[2] | i[3] | i[5] | i[7] | i[8] | i[11] | i[14] | i[20] | i[24] | i[25] | i[26];\n",[198,802,803],{"class":200,"line":417},[198,804,805],{},"    assign ALUC[1] = i[0] | i[2] | i[6] | i[7] | i[8] | i[9] | i[10] | i[13] | i[17] | i[21] | i[22] | i[23] | i[24] | i[25] | i[26] | i[27];\n",[198,807,808],{"class":200,"line":423},[198,809,810],{},"    assign ALUC[2] = i[4] | i[5] | i[6] | i[7] | i[10] | i[11] | i[12] | i[13] | i[14] | i[15] | i[19] | i[20] | i[21];\n",[198,812,813],{"class":200,"line":429},[198,814,815],{},"    assign ALUC[3] = i[8] | i[9] | i[10] | i[11] | i[12] | i[13] | i[14] | i[15] | i[26] | i[27] | i[28];\n",[198,817,818],{"class":200,"line":435},[198,819,820],{},"    assign RF_W = ~(i[16] | i[23] | i[24] | i[25] | i[29]);\n",[198,822,823],{"class":200,"line":441},[198,824,825],{},"    assign RF_CLK = ~clk;\n",[198,827,828],{"class":200,"line":447},[198,829,830],{},"    assign DM_w = i[23];\n",[198,832,833],{"class":200,"line":453},[198,834,835],{},"    assign DM_r = i[22];\n",[198,837,838],{"class":200,"line":459},[198,839,840],{},"    assign DM_cs = i[22] | i[23];\n",[198,842,843],{"class":200,"line":465},[198,844,845],{},"    assign C_EXT16 = ~(i[19] | i[20] | i[21]);\n",[198,847,848],{"class":200,"line":471},[198,849,474],{},[851,852,853],"style",{},"html .light .shiki span {color: var(--shiki-light);background: var(--shiki-light-bg);font-style: var(--shiki-light-font-style);font-weight: var(--shiki-light-font-weight);text-decoration: var(--shiki-light-text-decoration);}html.light .shiki span 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var(--shiki-dark-font-style);font-weight: var(--shiki-dark-font-weight);text-decoration: var(--shiki-dark-text-decoration);}",{"title":183,"searchDepth":201,"depth":207,"links":855},[856,857,858],{"id":152,"depth":207,"text":152},{"id":174,"depth":207,"text":174},{"id":477,"depth":207,"text":477},"详解31条MIPS单周期CPU的指令译码器和控制器Verilog代码实现，包括指令译码逻辑、控制器真值表实现、以及与数据通路的连接方式。","md",null,{"date":863},"2019-03-21 19:50:07",true,{"title":866,"description":867},"【verilog\u002Fmips】31条指令单周期cpu设计(Verilog)-(八)上代码→指令译码以及控制器","详细介绍31条MIPS单周期CPU的指令译码器和控制器Verilog代码实现方法，包含指令译码逻辑、控制器真值表实现、以及与数据通路的连接方式，适合Verilog CPU设计进阶学习。","xxDfWXGv8FxKupFqPqjt1MloS9KnfBWhf5OeFRBYSU4",[870,872],{"title":116,"path":117,"stem":118,"description":871,"children":-1},"详解31条MIPS单周期CPU的Verilog整体代码结构，包括顶层模块scpu、指令译码器cpu_ins、控制器cpu_opcode等模块的组织方式和连接关系。",{"title":124,"path":125,"stem":126,"description":873,"children":-1},"详解31条MIPS单周期CPU的基础模块Verilog代码实现，包括MUX、扩展器、加法器、ALU、寄存器堆等核心部件的代码实现。",1776616492711]