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run_native","\u002Frust\u002Fegui2","5.rust\u002F02.egui2",{"id":145,"title":100,"body":146,"description":1017,"extension":1018,"links":1019,"meta":1020,"navigation":1022,"path":101,"seo":1023,"stem":102,"__hash__":1026},"docs\u002F4.verilog\u002F03.mips3.md",{"type":147,"value":148,"toc":973},"minimark",[149,153,175,178,207,211,308,312,315,385,388,442,444,457,460,472,476,489,492,504,508,521,525,538,542,555,559,572,576,590,593,606,609,623,626,640,643,656,659,677,680,696,699,714,717,731,734,748,751,762,765,778,781,794,797,810,813,831,834,850,853,867,870,883,886,900,903,915,918,931,934,948,951,969],[150,151,152],"h2",{"id":152},"说在前面",[154,155,156],"blockquote",{},[157,158,159,163,166,169,172],"ul",{},[160,161,162],"li",{},"开发环境：Vivado",[160,164,165],{},"语言：Verilog",[160,167,168],{},"cpu框架：Mips",[160,170,171],{},"控制器：组合逻辑",[160,173,174],{},"鸽鸽鸽。。。",[150,176,177],{"id":177},"指令分析流程",[179,180,181,189,195,201],"ol",{},[160,182,183,184,188],{},"确定一条指令所需要的",[185,186,187],"strong",{},"具体操作"," ",[160,190,191,192,188],{},"分析该条指令中",[185,193,194],{},"涉及的部件",[160,196,197,198,188],{},"确定各个部件的",[185,199,200],{},"输入输出关系",[160,202,203,204,188],{},"画出",[185,205,206],{},"数据通路图",[208,209,210],"h3",{"id":210},"例子",[157,212,213,216,232,235,300],{},[160,214,215],{},"以ADD为例",[160,217,218,219,223,224,227,228,231],{},"首先我们需要根据PC从指令集合中取出这条指令，然后将两个操作数相加 R",[220,221,222],"span",{},"rd","→R",[220,225,226],{},"rs","+R",[220,229,230],{},"rt"," ，最后将PC+4，指向下一条指令；",[160,233,234],{},"涉及部件：PC寄存器、指令存储器、寄存器、ALU",[160,236,200,237],{},[238,239,240,241,240,278],"table",{},"\n  ",[242,243,244,245,244,267,240],"thead",{},"\n    ",[246,247,248,249,248,254,248,257,248,260,248,263,244],"tr",{},"\n      ",[250,251,253],"th",{"rowSpan":252},2,"指令",[250,255,256],{"rowSpan":252},"PC",[250,258,259],{"rowSpan":252},"IM",[250,261,262],{},"RF",[250,264,266],{"colSpan":265},"2","ALU",[246,268,248,269,248,272,248,275,244],{},[250,270,271],{},"WData",[250,273,274],{},"A",[250,276,277],{},"B",[279,280,244,281,240],"tbody",{},[246,282,248,283,248,287,248,290,248,292,248,294,248,297,244],{},[284,285,286],"td",{},"ADD",[284,288,289],{},"PC+4",[284,291,256],{},[284,293,266],{},[284,295,296],{},"RF.RD1",[284,298,299],{},"RF.RD2",[160,301,302,303],{},"数据通路图\n",[304,305],"img",{"alt":306,"src":307},"add",".\u002Fverilog\u002F6.webp",[150,309,311],{"id":310},"_31条指令分析","31条指令分析 ",[208,313,314],{"id":314},"字符说明",[238,316,244,317,240],{},[279,318,248,319,248,337,248,354,248,369,244],{},[246,320,321,322,321,325,321,328,321,331,321,334,248],{},"\n        ",[250,323,324],{},"NPC",[250,326,327],{},"IMEM",[250,329,330],{},"RegFiles",[250,332,333],{},"IR",[250,335,336],{},"DMEM",[246,338,321,339,321,342,321,345,321,348,321,351,248],{},[284,340,341],{},"即PC+4，可以使用简单的加法实现",[284,343,344],{},"指令存储器",[284,346,347],{},"寄存器堆",[284,349,350],{},"指令寄存器",[284,352,353],{},"数据存储器",[246,355,321,356,321,358,321,361,321,364,321,367,248],{},[250,357,256],{},[250,359,360],{},"ADD8",[250,362,363],{},"EXTn",[250,365,366],{},"MUX",[250,368],{},[246,370,321,371,321,374,321,377,321,380,321,383,248],{},[284,372,373],{},"指令计数器",[284,375,376],{},"加8操作",[284,378,379],{},"将n位扩展",[284,381,382],{},"多路选择器",[284,384],{},[208,386,387],{"id":387},"先放总结",[157,389,390,405,413,421,427],{},[160,391,392,393,398,399,404],{},"​在分析指令的时候一定要参考",[220,394,397],{"className":395},[396],"text-warning","详细的指令说明","，在",[400,401,403],"a",{"href":402},".\u002Fmips2","上一篇","中有，这样可以帮助理解指令过程；",[160,406,407,408,412],{},"这31条指令看似很多 ",[409,410,411],"del",{},"（其实真的很多）","，但是里面还是有很多是相似的，所以数据通路图几乎一样；",[160,414,415,416],{},"比较难的几条指令：",[220,417,420],{"className":418},[419],"text-secondary","lw、sw、jal、beq",[160,422,423,424],{},"建议自己分析一遍 ",[409,425,426],{},"（很重要）",[160,428,429,430,435,436,441],{},"下一篇将分析两张很大很大的表格，",[220,431,434],{"className":432},[433],"text-info","指令操作时间表以及整体数据输入输出关系表","，",[220,437,440],{"className":438},[439],"text-error","这两张表对于整体的数据通路的设计以及控制器设计十分重要！！！","\n​",[208,443,306],{"id":306},[157,445,446,449,452],{},[160,447,448],{},"格式：add rd, rs, rt",[160,450,451],{},"描述：rd ← rs + rt; PC ← NPC (PC + 4)",[160,453,454,455],{},"部件：PC、NPC、IMEN、RegFiles、ALU\n",[304,456],{"alt":306,"src":307},[208,458,459],{"id":459},"addu",[157,461,462,465,467],{},[160,463,464],{},"格式：addu rd, rs, rt",[160,466,451],{},[160,468,454,469],{},[304,470],{"alt":459,"src":471},".\u002Fverilog\u002F7.webp",[208,473,475],{"id":474},"sub","sub ",[157,477,478,481,484],{},[160,479,480],{},"格式：sub rd, rs, rt",[160,482,483],{},"描述：rd ← rs - rt; PC ← NPC (PC + 4)",[160,485,454,486],{},[304,487],{"alt":474,"src":488},".\u002Fverilog\u002F8.webp",[208,490,491],{"id":491},"subu",[157,493,494,497,499],{},[160,495,496],{},"格式：subu rd, rs, rt",[160,498,483],{},[160,500,454,501],{},[304,502],{"alt":491,"src":503},".\u002Fverilog\u002F9.webp",[208,505,507],{"id":506},"and"," and",[157,509,510,513,516],{},[160,511,512],{},"格式：and rd, rs, rt",[160,514,515],{},"描述：rd ← rs and rt; PC ← NPC (PC + 4)",[160,517,454,518],{},[304,519],{"alt":506,"src":520},".\u002Fverilog\u002F10.webp",[208,522,524],{"id":523},"or"," or",[157,526,527,530,533],{},[160,528,529],{},"格式：or rd, rs, rt",[160,531,532],{},"描述：rd ← rs or rt; PC ← NPC (PC + 4)",[160,534,454,535],{},[304,536],{"alt":523,"src":537},".\u002Fverilog\u002F11.webp",[208,539,541],{"id":540},"xor"," xor",[157,543,544,547,550],{},[160,545,546],{},"格式：xor rd, rs, rt",[160,548,549],{},"描述：rd ← rs xor rt; PC ← NPC (PC + 4)",[160,551,454,552],{},[304,553],{"alt":540,"src":554},".\u002Fverilog\u002F12.webp",[208,556,558],{"id":557},"nor"," nor",[157,560,561,564,567],{},[160,562,563],{},"格式：nor rd, rs, rt",[160,565,566],{},"描述：rd ← rs nor rt; PC ← NPC (PC + 4)",[160,568,454,569],{},[304,570],{"alt":557,"src":571},".\u002Fverilog\u002F13.webp",[208,573,575],{"id":574},"slt"," slt",[157,577,578,581,584],{},[160,579,580],{},"格式：slt rd, rs, rt",[160,582,583],{},"描述：rd ← (rs \u003C rt); PC ← NPC (PC + 4)",[160,585,586,587],{},"部件：PC、NPC、IMEN、RegFiles、ALU、EXT1\n",[304,588],{"alt":574,"src":589},".\u002Fverilog\u002F14.webp",[208,591,592],{"id":592},"sltu",[157,594,595,598,600],{},[160,596,597],{},"格式：sltu rd, rs, rt",[160,599,583],{},[160,601,602,603],{},"部件：PC、NPC、IMEN、RegFiles、ALU、EXT1 \n",[304,604],{"alt":592,"src":605},".\u002Fverilog\u002F15.webp",[208,607,608],{"id":608},"sll",[157,610,611,614,617],{},[160,612,613],{},"格式：sll rd, rt, sa",[160,615,616],{},"描述：rd ← rt \u003C\u003C sa (logical); PC ← NPC (PC + 4)",[160,618,619,620],{},"部件：PC、NPC、IMEN、RegFiles、ALU、Ext5 \n",[304,621],{"alt":608,"src":622},".\u002Fverilog\u002F16.webp",[208,624,625],{"id":625},"srl",[157,627,628,631,634],{},[160,629,630],{},"格式：srl rd, rt, sa",[160,632,633],{},"描述: rd ← rt >> sa (logical); PC ← NPC (PC + 4)",[160,635,636,637],{},"部件：PC、NPC、IMEN、RegFiles、ALU、Ext5\n",[304,638],{"alt":625,"src":639},".\u002Fverilog\u002F17.webp",[208,641,642],{"id":642},"sra",[157,644,645,648,651],{},[160,646,647],{},"格式：sra rd, rt, sa",[160,649,650],{},"描述: rd ← rt >> sa (arithmetic); PC ← NPC (PC + 4)",[160,652,636,653],{},[304,654],{"alt":642,"src":655},".\u002Fverilog\u002F18.webp",[208,657,658],{"id":658},"sllv",[157,660,661,664,671],{},[160,662,663],{},"格式：sllv rd, rt, rs",[160,665,666,667,670],{},"描述：rd ← rt \u003C\u003C rs ",[220,668,669],{},"4:0"," (logical); PC ← NPC (PC + 4)",[160,672,673,674],{},"部件：PC、NPC、IMEN、RegFiles、ALU、EXT5 \n",[304,675],{"alt":658,"src":676},".\u002Fverilog\u002F19.webp",[208,678,679],{"id":679},"srlv",[157,681,682,685,690],{},[160,683,684],{},"格式：srlv rd, rt, rs",[160,686,687,688,670],{},"描述：rd ← rt >> rs ",[220,689,669],{},[160,691,692,693],{},"部件：PC、NPC、IMEN、RegFiles、ALU、EXT5\n",[304,694],{"alt":679,"src":695},".\u002Fverilog\u002F20.webp",[208,697,698],{"id":698},"srav",[157,700,701,704,709],{},[160,702,703],{},"格式：srav rd, rt, rs",[160,705,687,706,708],{},[220,707,669],{}," (arithmetic); PC ← NPC (PC + 4)",[160,710,692,711],{},[304,712],{"alt":698,"src":713},".\u002Fverilog\u002F21.webp",[208,715,716],{"id":716},"jr",[157,718,719,722,725],{},[160,720,721],{},"格式：jr rs",[160,723,724],{},"描述：PC ← rs; PC ← NPC (PC + 4)",[160,726,727,728],{},"部件：PC、NPC、IMEN、RegFiles \n",[304,729],{"alt":716,"src":730},".\u002Fverilog\u002F22.webp",[208,732,733],{"id":733},"addi",[157,735,736,739,742],{},[160,737,738],{},"格式：addi rt, rs, immediate",[160,740,741],{},"描述：rt ← rs + immediate; PC ← NPC (PC + 4)",[160,743,744,745],{},"部件：PC、NPC、IMEN、RegFiles、ALU、EXT16\n",[304,746],{"alt":733,"src":747},".\u002Fverilog\u002F24.webp",[208,749,750],{"id":750},"addiu",[157,752,753,756,758],{},[160,754,755],{},"格式：addiu rt, rs, immediate",[160,757,741],{},[160,759,744,760],{},[304,761],{"alt":750,"src":747},[208,763,764],{"id":764},"andi",[157,766,767,770,773],{},[160,768,769],{},"格式：andi rt, rs, immediate",[160,771,772],{},"描述：rt ← rs and immediate; PC ← NPC (PC + 4)",[160,774,744,775],{},[304,776],{"alt":764,"src":777},".\u002Fverilog\u002F25.webp",[208,779,780],{"id":780},"ori",[157,782,783,786,789],{},[160,784,785],{},"格式：ori rt, rs, immediate",[160,787,788],{},"描述：rt ← rs or immediate; PC ← NPC (PC + 4)",[160,790,744,791],{},[304,792],{"alt":780,"src":793},".\u002Fverilog\u002F26.webp",[208,795,796],{"id":796},"xori",[157,798,799,802,805],{},[160,800,801],{},"格式：xori rt, rs, immediate",[160,803,804],{},"描述：rt ← rs xor immediate; PC ← NPC (PC + 4)",[160,806,744,807],{},[304,808],{"alt":796,"src":809},".\u002Fverilog\u002F27.webp",[208,811,812],{"id":812},"lw",[157,814,815,818,825],{},[160,816,817],{},"格式：lw rt, offset(base)",[160,819,820,821,824],{},"描述：rt ← memory",[220,822,823],{},"rs + Sign_ext_offset","; PC ← NPC (PC + 4)",[160,826,827,828],{},"部件：PC、NPC、IMEN、RegFiles、ALU、EXT16、DMEM\n",[304,829],{"alt":812,"src":830},".\u002Fverilog\u002F28.webp",[208,832,833],{"id":833},"sw",[157,835,836,839,845],{},[160,837,838],{},"格式：sw rt, offset(base)",[160,840,841,842,844],{},"描述：memory",[220,843,823],{}," ← rt; PC ← NPC (PC + 4)",[160,846,827,847],{},[304,848],{"alt":833,"src":849},".\u002Fverilog\u002F29.webp",[208,851,852],{"id":852},"beq",[157,854,855,858,861],{},[160,856,857],{},"格式：beq rs, rt, offset",[160,859,860],{},"描述：rs == rt, PC ← NPC + Sign_ext (offset||02)；否则PC ← NPC(PC+4)",[160,862,863,864],{},"部件：PC、NPC、IMEN、RegFiles、ALU、EXT18、ADD\n",[304,865],{"alt":852,"src":866},".\u002Fverilog\u002F30.webp",[208,868,869],{"id":869},"bne",[157,871,872,875,878],{},[160,873,874],{},"格式：bne rs, rt, offset",[160,876,877],{},"描述：rs != rt, PC ← NPC + Sign_ext (offset||02)；否则PC ← NPC(PC+4)",[160,879,863,880],{},[304,881],{"alt":869,"src":882},".\u002Fverilog\u002F31.webp",[208,884,885],{"id":885},"slti",[157,887,888,891,894],{},[160,889,890],{},"格式：slti rt, rs, immediate",[160,892,893],{},"描述：rt ← (rs \u003C immediate); PC ← NPC(PC+4)",[160,895,896,897],{},"部件：PC、NPC、IMEN、RegFiles、ALU、EXT16、EXT1\n",[304,898],{"alt":885,"src":899},".\u002Fverilog\u002F32.webp",[208,901,902],{"id":902},"sltiu",[157,904,905,908,910],{},[160,906,907],{},"格式：sltiu rt, rs, immediate",[160,909,893],{},[160,911,896,912],{},[304,913],{"alt":902,"src":914},".\u002Fverilog\u002F33.webp",[208,916,917],{"id":917},"lui",[157,919,920,923,926],{},[160,921,922],{},"格式：lui rt, immediate",[160,924,925],{},"描述：rt ← immediate || 016; PC ← NPC(PC+4)",[160,927,744,928],{},[304,929],{"alt":917,"src":930},".\u002Fverilog\u002F34.webp",[208,932,933],{"id":933},"j",[157,935,936,939,942],{},[160,937,938],{},"格式：j target",[160,940,941],{},"描述：PC ← PC31-28 || instr_index || 02; PC ← NPC(PC+4)",[160,943,944,945],{},"部件：PC、NPC、IMEN、ALU、II\n",[304,946],{"alt":933,"src":947},".\u002Fverilog\u002F35.webp",[208,949,950],{"id":950},"jal",[157,952,953,956,963],{},[160,954,955],{},"格式：jal target",[160,957,958,959,962],{},"描述：GPR",[220,960,961],{},"31"," ← PC + 8；PC ← PC31-28 || instr_index || 02；PC ← NPC(PC+4)",[160,964,965,966],{},"部件：PC、NPC、IMEN、RegFiles、ALU、II、ADD8\n",[304,967],{"alt":950,"src":968},".\u002Fverilog\u002F36.webp",[970,971,972],"p",{},"​",{"title":974,"searchDepth":975,"depth":252,"links":976},"",1,[977,978,982],{"id":152,"depth":252,"text":152},{"id":177,"depth":252,"text":177,"children":979},[980],{"id":210,"depth":981,"text":210},3,{"id":310,"depth":252,"text":311,"children":983},[984,985,986,987,988,989,990,991,992,993,994,995,996,997,998,999,1000,1001,1002,1003,1004,1005,1006,1007,1008,1009,1010,1011,1012,1013,1014,1015,1016],{"id":314,"depth":981,"text":314},{"id":387,"depth":981,"text":387},{"id":306,"depth":981,"text":306},{"id":459,"depth":981,"text":459},{"id":474,"depth":981,"text":475},{"id":491,"depth":981,"text":491},{"id":506,"depth":981,"text":507},{"id":523,"depth":981,"text":524},{"id":540,"depth":981,"text":541},{"id":557,"depth":981,"text":558},{"id":574,"depth":981,"text":575},{"id":592,"depth":981,"text":592},{"id":608,"depth":981,"text":608},{"id":625,"depth":981,"text":625},{"id":642,"depth":981,"text":642},{"id":658,"depth":981,"text":658},{"id":679,"depth":981,"text":679},{"id":698,"depth":981,"text":698},{"id":716,"depth":981,"text":716},{"id":733,"depth":981,"text":733},{"id":750,"depth":981,"text":750},{"id":764,"depth":981,"text":764},{"id":780,"depth":981,"text":780},{"id":796,"depth":981,"text":796},{"id":812,"depth":981,"text":812},{"id":833,"depth":981,"text":833},{"id":852,"depth":981,"text":852},{"id":869,"depth":981,"text":869},{"id":885,"depth":981,"text":885},{"id":902,"depth":981,"text":902},{"id":917,"depth":981,"text":917},{"id":933,"depth":981,"text":933},{"id":950,"depth":981,"text":950},"详细分析31条MIPS指令的数据通路设计，包括ADD、SUB、LW、SW、JAL等指令的部件需求、输入输出关系和数据通路图，附完整Verilog实现参考。","md",null,{"date":1021},"2018-07-14 11:27:27",true,{"title":1024,"description":1025},"【verilog\u002Fmips】31条指令单周期cpu设计(Verilog)-(三)指令分析","逐条分析31条MIPS单周期CPU指令的数据通路设计，包含ADD、SUB、LW、SW、BEQ、JAL等指令的部件连接图和Verilog代码实现，计算机组成原理课程必备。","0X7MDDwHcYKTeaeiwbhDOHJs-aIyQw1R-gKi_Q17V7s",[1028,1030],{"title":96,"path":97,"stem":98,"description":1029,"children":-1},"详解31条MIPS指令单周期CPU的总体设计方案，包括指令分类、数据通路设计、控制器设计流程，以及lw、sw、jal等难点指令的处理思路。",{"title":104,"path":105,"stem":106,"description":1031,"children":-1},"详解31条MIPS指令数据通路设计中各部件的输入输出关系表，包含PC、NPC、ALU、寄存器堆等部件的详细连接关系，用于Verilog代码结构设计。",1776616491898]