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reset,\n    input  [31:0] inst,\n    input  [31:0] rdata,\n    output [31:0] pc,\n    output [31:0] addr,\n    output [31:0] wdata,\n    output        IM_R,\n    output        DM_CS,\n    output        DM_R,\n    output        DM_W\n    );\n    \u002F\u002F--------------------------------\u002F\u002F控制信号(除有关存储器）\n    wire PC_CLK;                     \u002F\u002F\n    wire PC_ENA;                     \u002F\u002F\n    wire M1;                         \u002F\u002F\n    wire M2;                         \u002F\u002F\n    wire M3;                         \u002F\u002F\n    wire M4;                         \u002F\u002F\n    wire M5;                         \u002F\u002F\n    wire M6;                         \u002F\u002F\n    wire M7;                         \u002F\u002F\n    wire M8;                         \u002F\u002F\n    wire M9;                         \u002F\u002F\n    wire M10;                        \u002F\u002F\n    wire M11;                        \u002F\u002F\n    wire [3:0] ALUC;                 \u002F\u002F\n    wire RF_W;                       \u002F\u002F\n    wire RF_CLK;                     \u002F\u002F\n    wire C_EXT16;                    \u002F\u002F\n    \u002F\u002F--------------------------------\u002F\u002F运算标志位\n    wire zero;                       \u002F\u002F\n    wire carry;                      \u002F\u002F\n    wire negative;                   \u002F\u002F\n    wire overflow;                   \u002F\u002F\n    wire add_overflow;               \u002F\u002F\n    \u002F\u002F--------------------------------\u002F\u002F \n    wire [31:0] INS;                 \u002F\u002F译码后指令\n    \u002F\u002F--------------------------------\u002F\u002F数据通路（除有关存储器）\n    wire [31:0] D_ALU;               \u002F\u002F\n    wire [31:0] D_PC;                \u002F\u002F\n    wire [31:0] D_RF;                \u002F\u002F\n    wire [31:0] D_Rs;                \u002F\u002F\n    wire [31:0] D_Rt;                \u002F\u002F\n    wire [31:0] D_IM;                \u002F\u002F\n    wire [31:0] D_DM;                \u002F\u002F\n    wire [31:0] D_Mux1;              \u002F\u002F\n    wire [31:0] D_Mux2;              \u002F\u002F\n    wire [31:0] D_Mux3;              \u002F\u002F\n    wire [4:0]  D_Mux4;              \u002F\u002F\n    wire [4:0]  D_Mux5;              \u002F\u002F\n    wire [31:0] D_Mux6;              \u002F\u002F\n    wire [31:0] D_Mux7;              \u002F\u002F\n    wire [31:0] D_Mux8;              \u002F\u002F\n    wire [31:0] D_Mux9;              \u002F\u002F\n    wire [31:0] D_Mux10;             \u002F\u002F\n    wire        D_Mux11;             \u002F\u002F\n                                      \u002F\u002F\n    wire [31:0] D_EXT1;              \u002F\u002F\n    wire [31:0] D_EXT5;              \u002F\u002F\n    wire [31:0] D_EXT16;             \u002F\u002F\n    wire [31:0] D_EXT18;             \u002F\u002F\n    wire [31:0] D_ADD;               \u002F\u002F\n    wire [31:0] D_ADD8;              \u002F\u002F\n    wire [31:0] D_NPC;               \u002F\u002F\n    wire [31:0] D_ii;                \u002F\u002F\n    assign PC_ENA = 1;\n    \u002F\u002F--------------------------------\u002F\u002F外部通路连接\n    assign pc = D_PC;\n    assign addr = D_ALU;\n    assign wdata = D_Rt;\n    \n    \u002F\u002F--------------------------------\u002F\u002F指令译码\n    instr_dec cpu_ins (inst, INS);\n    operation cpu_opcode (clk,zero,INS,PC_CLK,IM_R,M1,M2,M3,M4,M5,M6,M7,M9,  M10,ALUC,RF_W,RF_CLK,DM_W,DM_R,DM_CS,C_EXT16);\n    \u002F\u002F--------------------------------\u002F\u002F部件\n    pcreg   pc_out      (PC_CLK,     reset,      PC_ENA,      D_Mux1,     D_PC);\n    alu     cpu_alu     (D_Mux9,     D_Mux10,    ALUC[3:0],   D_ALU,      zero,         carry,        negative, overflow);\n    regfile cpu_ref     (RF_CLK,     reset,      RF_W,        overflow, inst  [25:21],  inst[20:16],  D_Mux5,   D_Mux6,D_Rs, D_Rt);\n    mux     cpu_mux1    (D_Mux3,     D_Mux2,     M1,          D_Mux1);\n    mux     cpu_mux2    (D_NPC,      D_ADD,      M2,          D_Mux2);\n    mux     cpu_mux3    (D_ii,       D_Rs,       M3,          D_Mux3);\n    mux5    cpu_mux4    (inst[10:6], D_Rs[4:0],  {INS[30],M4},D_Mux4);\n    mux5    cpu_mux5    (inst[15:11],inst[20:16],{INS[30],M5},D_Mux5);\n    mux     cpu_mux6    (D_Mux7,     D_ADD8,     M6,          D_Mux6);\n    mux     cpu_mux7    (D_ALU,     rdata,      M7,          D_Mux7);\n    mux     cpu_mux9    (D_EXT5,     D_Rs,       M9,          D_Mux9);\n    mux     cpu_mux10   (D_Rt,       D_EXT16,    M10,         D_Mux10);\n    extend5 cpu_ext5    (D_Mux4,     D_EXT5);\n    extend16 cpu_ext16  (inst[15:0], C_EXT16,    D_EXT16);\n    extend18 cpu_ext18  (inst[15:0], D_EXT18);\n    add     cpu_add     (D_EXT18,    D_NPC,      D_ADD,       add_overflow);\n    add8    cpu_add8    (D_PC,       D_ADD8);\n    npc     cpu_npc     (D_PC,       reset,      D_NPC);\n    II      cpu_ii      (D_PC[31:28],inst[25:0], D_ii);\n    \nendmodule\n","verilog","",[195,196,197,204,210,216,222,228,234,240,246,252,258,264,270,276,282,288,294,300,306,312,318,324,330,336,342,348,354,360,366,372,378,384,390,396,402,408,414,420,426,432,438,444,450,456,462,468,474,480,486,492,498,504,510,516,522,528,534,540,546,552,558,564,570,576,582,588,594,600,606,612,618,624,630,636,642,648,654,660,666,672,678,684,690,696,702,708,714,720,726,732,738,744,750,756,762,768,774,780,785],"code",{"__ignoreMap":193},[181,198,201],{"class":199,"line":200},"line",1,[181,202,203],{},"`timescale 1ns \u002F 1ps\n",[181,205,207],{"class":199,"line":206},2,[181,208,209],{},"module cpu(\n",[181,211,213],{"class":199,"line":212},3,[181,214,215],{},"    input         clk,\n",[181,217,219],{"class":199,"line":218},4,[181,220,221],{},"    input         reset,\n",[181,223,225],{"class":199,"line":224},5,[181,226,227],{},"    input  [31:0] inst,\n",[181,229,231],{"class":199,"line":230},6,[181,232,233],{},"    input  [31:0] rdata,\n",[181,235,237],{"class":199,"line":236},7,[181,238,239],{},"    output [31:0] pc,\n",[181,241,243],{"class":199,"line":242},8,[181,244,245],{},"    output [31:0] addr,\n",[181,247,249],{"class":199,"line":248},9,[181,250,251],{},"    output [31:0] wdata,\n",[181,253,255],{"class":199,"line":254},10,[181,256,257],{},"    output        IM_R,\n",[181,259,261],{"class":199,"line":260},11,[181,262,263],{},"    output        DM_CS,\n",[181,265,267],{"class":199,"line":266},12,[181,268,269],{},"    output        DM_R,\n",[181,271,273],{"class":199,"line":272},13,[181,274,275],{},"    output        DM_W\n",[181,277,279],{"class":199,"line":278},14,[181,280,281],{},"    );\n",[181,283,285],{"class":199,"line":284},15,[181,286,287],{},"    \u002F\u002F--------------------------------\u002F\u002F控制信号(除有关存储器）\n",[181,289,291],{"class":199,"line":290},16,[181,292,293],{},"    wire PC_CLK;                     \u002F\u002F\n",[181,295,297],{"class":199,"line":296},17,[181,298,299],{},"    wire PC_ENA;                     \u002F\u002F\n",[181,301,303],{"class":199,"line":302},18,[181,304,305],{},"    wire M1;                         \u002F\u002F\n",[181,307,309],{"class":199,"line":308},19,[181,310,311],{},"    wire M2;                         \u002F\u002F\n",[181,313,315],{"class":199,"line":314},20,[181,316,317],{},"    wire M3;                         \u002F\u002F\n",[181,319,321],{"class":199,"line":320},21,[181,322,323],{},"    wire M4;                         \u002F\u002F\n",[181,325,327],{"class":199,"line":326},22,[181,328,329],{},"    wire M5;                         \u002F\u002F\n",[181,331,333],{"class":199,"line":332},23,[181,334,335],{},"    wire M6;                         \u002F\u002F\n",[181,337,339],{"class":199,"line":338},24,[181,340,341],{},"    wire M7;                         \u002F\u002F\n",[181,343,345],{"class":199,"line":344},25,[181,346,347],{},"    wire M8;                         \u002F\u002F\n",[181,349,351],{"class":199,"line":350},26,[181,352,353],{},"    wire M9;                         \u002F\u002F\n",[181,355,357],{"class":199,"line":356},27,[181,358,359],{},"    wire M10;                        \u002F\u002F\n",[181,361,363],{"class":199,"line":362},28,[181,364,365],{},"    wire M11;                        \u002F\u002F\n",[181,367,369],{"class":199,"line":368},29,[181,370,371],{},"    wire [3:0] ALUC;                 \u002F\u002F\n",[181,373,375],{"class":199,"line":374},30,[181,376,377],{},"    wire RF_W;                       \u002F\u002F\n",[181,379,381],{"class":199,"line":380},31,[181,382,383],{},"    wire RF_CLK;                     \u002F\u002F\n",[181,385,387],{"class":199,"line":386},32,[181,388,389],{},"    wire C_EXT16;                    \u002F\u002F\n",[181,391,393],{"class":199,"line":392},33,[181,394,395],{},"    \u002F\u002F--------------------------------\u002F\u002F运算标志位\n",[181,397,399],{"class":199,"line":398},34,[181,400,401],{},"    wire zero;                       \u002F\u002F\n",[181,403,405],{"class":199,"line":404},35,[181,406,407],{},"    wire carry;                      \u002F\u002F\n",[181,409,411],{"class":199,"line":410},36,[181,412,413],{},"    wire negative;                   \u002F\u002F\n",[181,415,417],{"class":199,"line":416},37,[181,418,419],{},"    wire overflow;                   \u002F\u002F\n",[181,421,423],{"class":199,"line":422},38,[181,424,425],{},"    wire add_overflow;               \u002F\u002F\n",[181,427,429],{"class":199,"line":428},39,[181,430,431],{},"    \u002F\u002F--------------------------------\u002F\u002F \n",[181,433,435],{"class":199,"line":434},40,[181,436,437],{},"    wire [31:0] INS;                 \u002F\u002F译码后指令\n",[181,439,441],{"class":199,"line":440},41,[181,442,443],{},"    \u002F\u002F--------------------------------\u002F\u002F数据通路（除有关存储器）\n",[181,445,447],{"class":199,"line":446},42,[181,448,449],{},"    wire [31:0] D_ALU;               \u002F\u002F\n",[181,451,453],{"class":199,"line":452},43,[181,454,455],{},"    wire [31:0] D_PC;                \u002F\u002F\n",[181,457,459],{"class":199,"line":458},44,[181,460,461],{},"    wire [31:0] D_RF;                \u002F\u002F\n",[181,463,465],{"class":199,"line":464},45,[181,466,467],{},"    wire [31:0] D_Rs;                \u002F\u002F\n",[181,469,471],{"class":199,"line":470},46,[181,472,473],{},"    wire [31:0] D_Rt;                \u002F\u002F\n",[181,475,477],{"class":199,"line":476},47,[181,478,479],{},"    wire [31:0] D_IM;                \u002F\u002F\n",[181,481,483],{"class":199,"line":482},48,[181,484,485],{},"    wire [31:0] D_DM;                \u002F\u002F\n",[181,487,489],{"class":199,"line":488},49,[181,490,491],{},"    wire [31:0] D_Mux1;              \u002F\u002F\n",[181,493,495],{"class":199,"line":494},50,[181,496,497],{},"    wire [31:0] D_Mux2;              \u002F\u002F\n",[181,499,501],{"class":199,"line":500},51,[181,502,503],{},"    wire [31:0] D_Mux3;              \u002F\u002F\n",[181,505,507],{"class":199,"line":506},52,[181,508,509],{},"    wire [4:0]  D_Mux4;              \u002F\u002F\n",[181,511,513],{"class":199,"line":512},53,[181,514,515],{},"    wire [4:0]  D_Mux5;              \u002F\u002F\n",[181,517,519],{"class":199,"line":518},54,[181,520,521],{},"    wire [31:0] D_Mux6;              \u002F\u002F\n",[181,523,525],{"class":199,"line":524},55,[181,526,527],{},"    wire [31:0] D_Mux7;              \u002F\u002F\n",[181,529,531],{"class":199,"line":530},56,[181,532,533],{},"    wire [31:0] D_Mux8;              \u002F\u002F\n",[181,535,537],{"class":199,"line":536},57,[181,538,539],{},"    wire [31:0] D_Mux9;              \u002F\u002F\n",[181,541,543],{"class":199,"line":542},58,[181,544,545],{},"    wire [31:0] D_Mux10;             \u002F\u002F\n",[181,547,549],{"class":199,"line":548},59,[181,550,551],{},"    wire        D_Mux11;             \u002F\u002F\n",[181,553,555],{"class":199,"line":554},60,[181,556,557],{},"                                      \u002F\u002F\n",[181,559,561],{"class":199,"line":560},61,[181,562,563],{},"    wire [31:0] D_EXT1;              \u002F\u002F\n",[181,565,567],{"class":199,"line":566},62,[181,568,569],{},"    wire [31:0] D_EXT5;              \u002F\u002F\n",[181,571,573],{"class":199,"line":572},63,[181,574,575],{},"    wire [31:0] D_EXT16;             \u002F\u002F\n",[181,577,579],{"class":199,"line":578},64,[181,580,581],{},"    wire [31:0] D_EXT18;             \u002F\u002F\n",[181,583,585],{"class":199,"line":584},65,[181,586,587],{},"    wire [31:0] D_ADD;               \u002F\u002F\n",[181,589,591],{"class":199,"line":590},66,[181,592,593],{},"    wire [31:0] D_ADD8;              \u002F\u002F\n",[181,595,597],{"class":199,"line":596},67,[181,598,599],{},"    wire [31:0] D_NPC;               \u002F\u002F\n",[181,601,603],{"class":199,"line":602},68,[181,604,605],{},"    wire [31:0] D_ii;                \u002F\u002F\n",[181,607,609],{"class":199,"line":608},69,[181,610,611],{},"    assign PC_ENA = 1;\n",[181,613,615],{"class":199,"line":614},70,[181,616,617],{},"    \u002F\u002F--------------------------------\u002F\u002F外部通路连接\n",[181,619,621],{"class":199,"line":620},71,[181,622,623],{},"    assign pc = D_PC;\n",[181,625,627],{"class":199,"line":626},72,[181,628,629],{},"    assign addr = D_ALU;\n",[181,631,633],{"class":199,"line":632},73,[181,634,635],{},"    assign wdata = D_Rt;\n",[181,637,639],{"class":199,"line":638},74,[181,640,641],{},"    \n",[181,643,645],{"class":199,"line":644},75,[181,646,647],{},"    \u002F\u002F--------------------------------\u002F\u002F指令译码\n",[181,649,651],{"class":199,"line":650},76,[181,652,653],{},"    instr_dec cpu_ins (inst, INS);\n",[181,655,657],{"class":199,"line":656},77,[181,658,659],{},"    operation cpu_opcode (clk,zero,INS,PC_CLK,IM_R,M1,M2,M3,M4,M5,M6,M7,M9,  M10,ALUC,RF_W,RF_CLK,DM_W,DM_R,DM_CS,C_EXT16);\n",[181,661,663],{"class":199,"line":662},78,[181,664,665],{},"    \u002F\u002F--------------------------------\u002F\u002F部件\n",[181,667,669],{"class":199,"line":668},79,[181,670,671],{},"    pcreg   pc_out      (PC_CLK,     reset,      PC_ENA,      D_Mux1,     D_PC);\n",[181,673,675],{"class":199,"line":674},80,[181,676,677],{},"    alu     cpu_alu     (D_Mux9,     D_Mux10,    ALUC[3:0],   D_ALU,      zero,         carry,        negative, overflow);\n",[181,679,681],{"class":199,"line":680},81,[181,682,683],{},"    regfile cpu_ref     (RF_CLK,     reset,      RF_W,        overflow, inst  [25:21],  inst[20:16],  D_Mux5,   D_Mux6,D_Rs, D_Rt);\n",[181,685,687],{"class":199,"line":686},82,[181,688,689],{},"    mux     cpu_mux1    (D_Mux3,     D_Mux2,     M1,          D_Mux1);\n",[181,691,693],{"class":199,"line":692},83,[181,694,695],{},"    mux     cpu_mux2    (D_NPC,      D_ADD,      M2,          D_Mux2);\n",[181,697,699],{"class":199,"line":698},84,[181,700,701],{},"    mux     cpu_mux3    (D_ii,       D_Rs,       M3,          D_Mux3);\n",[181,703,705],{"class":199,"line":704},85,[181,706,707],{},"    mux5    cpu_mux4    (inst[10:6], D_Rs[4:0],  {INS[30],M4},D_Mux4);\n",[181,709,711],{"class":199,"line":710},86,[181,712,713],{},"    mux5    cpu_mux5    (inst[15:11],inst[20:16],{INS[30],M5},D_Mux5);\n",[181,715,717],{"class":199,"line":716},87,[181,718,719],{},"    mux     cpu_mux6    (D_Mux7,     D_ADD8,     M6,          D_Mux6);\n",[181,721,723],{"class":199,"line":722},88,[181,724,725],{},"    mux     cpu_mux7    (D_ALU,     rdata,      M7,          D_Mux7);\n",[181,727,729],{"class":199,"line":728},89,[181,730,731],{},"    mux     cpu_mux9    (D_EXT5,     D_Rs,       M9,          D_Mux9);\n",[181,733,735],{"class":199,"line":734},90,[181,736,737],{},"    mux     cpu_mux10   (D_Rt,       D_EXT16,    M10,         D_Mux10);\n",[181,739,741],{"class":199,"line":740},91,[181,742,743],{},"    extend5 cpu_ext5    (D_Mux4,     D_EXT5);\n",[181,745,747],{"class":199,"line":746},92,[181,748,749],{},"    extend16 cpu_ext16  (inst[15:0], C_EXT16,    D_EXT16);\n",[181,751,753],{"class":199,"line":752},93,[181,754,755],{},"    extend18 cpu_ext18  (inst[15:0], D_EXT18);\n",[181,757,759],{"class":199,"line":758},94,[181,760,761],{},"    add     cpu_add     (D_EXT18,    D_NPC,      D_ADD,       add_overflow);\n",[181,763,765],{"class":199,"line":764},95,[181,766,767],{},"    add8    cpu_add8    (D_PC,       D_ADD8);\n",[181,769,771],{"class":199,"line":770},96,[181,772,773],{},"    npc     cpu_npc     (D_PC,       reset,      D_NPC);\n",[181,775,777],{"class":199,"line":776},97,[181,778,779],{},"    II      cpu_ii      (D_PC[31:28],inst[25:0], D_ii);\n",[181,781,783],{"class":199,"line":782},98,[181,784,641],{},[181,786,788],{"class":199,"line":787},99,[181,789,790],{},"endmodule\n",[150,792,793],{"id":793},"总结",[157,795,796],{},[160,797,798,799,803],{},"总算把鸽的写完了，我觉得这个系列的",[181,800,802],{"className":801},[184],"重点在前面的设计部分","，后面的代码可以自己写，只要掌握了整个流程写起来还是挺简单的，就是工作量很大，如果想要自己写的话就看前面几篇即可，代码部分可以不看了。",[805,806,807],"style",{},"html .light .shiki span {color: var(--shiki-light);background: var(--shiki-light-bg);font-style: var(--shiki-light-font-style);font-weight: var(--shiki-light-font-weight);text-decoration: var(--shiki-light-text-decoration);}html.light .shiki span {color: var(--shiki-light);background: var(--shiki-light-bg);font-style: var(--shiki-light-font-style);font-weight: var(--shiki-light-font-weight);text-decoration: var(--shiki-light-text-decoration);}html .default .shiki span {color: var(--shiki-default);background: var(--shiki-default-bg);font-style: var(--shiki-default-font-style);font-weight: var(--shiki-default-font-weight);text-decoration: var(--shiki-default-text-decoration);}html .shiki span {color: var(--shiki-default);background: var(--shiki-default-bg);font-style: var(--shiki-default-font-style);font-weight: var(--shiki-default-font-weight);text-decoration: var(--shiki-default-text-decoration);}html .dark .shiki span {color: var(--shiki-dark);background: var(--shiki-dark-bg);font-style: var(--shiki-dark-font-style);font-weight: var(--shiki-dark-font-weight);text-decoration: var(--shiki-dark-text-decoration);}html.dark .shiki span {color: var(--shiki-dark);background: var(--shiki-dark-bg);font-style: var(--shiki-dark-font-style);font-weight: var(--shiki-dark-font-weight);text-decoration: var(--shiki-dark-text-decoration);}",{"title":193,"searchDepth":200,"depth":206,"links":809},[810,811,812],{"id":152,"depth":206,"text":152},{"id":174,"depth":206,"text":174},{"id":793,"depth":206,"text":793},"详解31条MIPS单周期CPU的顶层模块Verilog代码实现，包括模块连接方式、控制信号设计、以及整个CPU设计流程的总结。","md",null,{"date":817},"2019-03-21 20:14:43",true,{"title":820,"description":821},"【verilog\u002Fmips】31条指令单周期cpu设计(Verilog)-(十)上代码→顶层模块设计&总结","详细介绍31条MIPS单周期CPU的顶层模块Verilog代码实现方法，包含模块连接方式、控制信号设计、以及整个CPU设计流程的总结，适合Verilog CPU设计完整学习。","vpKLbR5TTt599fBxSoyB7TDsICAZjfZ-Hi2NYUdMEhQ",[824,826],{"title":124,"path":125,"stem":126,"description":825,"children":-1},"详解31条MIPS单周期CPU的基础模块Verilog代码实现，包括MUX、扩展器、加法器、ALU、寄存器堆等核心部件的代码实现。",{"title":137,"path":138,"stem":139,"description":827,"children":-1},"Rust egui GUI 框架入门教程，介绍 eframe_template 项目克隆、编译运行、项目名称修改以及 WebAssembly 构建与 trunk 部署流程。",1776616492733]